Zobrazeno 1 - 10 of 573 pro vyhledávání: '"Hideo FUJIWARA"'
1
On the virtuous circle and vicious circle between the labor share and economic growth rate in neo-classical model and Keynesian model
Autor: Hideo, Fujiwara
Publikováno v: 同志社商学 = Doshisha Shogaku (The Doshisha Business Review). 74(2):249-279
経済成長率と労働分配率の間の好循環及び悪循環について、新古典派モデルとケインズ派モデルの分析の異同について論じている。
The paper analysis on the virtuous and vicious circles between the
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=jairo_______::6212aeee3c0151472fac4952e0f8bf76
http://id.nii.ac.jp/1707/00029298/
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3
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing
Autor: Hideo Fujiwara, Krishnendu Chakrabarty, Dong Xiang
Publikováno v: ACM Transactions on Design Automation of Electronic Systems. 23:1-23
We present a unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test deli
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::93bd8df5f51a4e6b99625bffed7ac7cd
https://doi.org/10.1145/3243214
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4
A Test Generation Method Based on k-Cycle Testing for Finite State Machines
Autor: Toshinori Hosokawa, Yuya Kinoshita, Hideo Fujiwara
Publikováno v: IOLTS
Scan testing requires long test application time and a large hardware overhead. To avoid these disadvantages, design-for-testability methods at register transfer level based on non-scan testing are important. We assume that controllers and data paths
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::29d560457da692f184cfc5e211795a49
https://doi.org/10.1109/iolts.2019.8854426
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6
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip
Autor: Krishnendu Chakrabarty, Dong Xiang, Hideo Fujiwara
Publikováno v: IEEE Transactions on Computers. 65:2767-2779
A 3D stacked network-on-chip (NOC) promises the integration of a large number of cores in a many-core system-on-chip (SOC). The NOC can be used to test the embedded cores in such SOCs, whereby the added cost of dedicated test-access hardware can be a
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b91ea921e0b35a1787df28d255daf7e2
https://doi.org/10.1109/tc.2015.2493548
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9
One More Class of Sequential Circuits having Combinational Test Generation Complexity
Autor: Debesh K. Das, Hideo Fujiwara
Publikováno v: Journal of Electronic Testing. 31:321-327
The paper uses the concept of time expansion model to find the test generation for acyclic sequential circuits. Any acyclic sequential circuit without hold registers can be tested with combinational test generation complexity using this model. We sho
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cc0cf815e5e9e813935367d460b96f96
https://doi.org/10.1007/s10836-015-5527-3
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