Výsledky vyhledávání - "Hidenari Nakashima"

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

Autor: Takashi Sato, Hiroo Masuda, Tsuyoshi Sakata, Takaaki Okumura, Toshiki Kanamoto, Nobuto Ono, Hidenari Nakashima, Masanori Hashimoto, Atsushi Kurokawa, Hiroshi Takafuji

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :990-997

SUMMARY Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::801907e091e541b52a368d0907346707
https://doi.org/10.1587/transfun.e92.a.990

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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability

Autor: Masakazu Tanaka, Koutaro Hachiya, Atsushi Kurokawa, Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Masanori Hashimoto, Hidenari Nakashima, Tsuyoshi Sakata, Hiroshi Takafuji, Hiroo Masuda, Takashi Sato

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3016-3023

Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate del

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d1f05e2f488d30fabce6e1e9e63e6fbd
https://doi.org/10.1587/transfun.e92.a.3016

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Proposal of Metrics for SSTA Accuracy Evaluation

Autor: Nobuto Ono, Hiroyuki Kobayashi, Takaaki Okumura, Jiro Iwai, Hidenari Nakashima, Takashi Sato, Masanori Hashimoto

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :808-814

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a prom

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9b18fd663ec85b27005ff82573521491
https://doi.org/10.1093/ietfec/e90-a.4.808

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Fast Methods to Estimate Clock Jitter due to Power Supply Noise

Autor: Hidenari Nakashima, Koutaro Hachiya, Masaaki Soda, Takayuki Ohshima, Satoshi Goto

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :741-747

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ef55fa92472da8af11d4d4884003d5df
https://doi.org/10.1093/ietfec/e90-a.4.741

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Optimization Methodology of Layer Numbers with Circuit/Process Co-Design

Autor: Junpei Inoue, Hidenari Nakashima, Kazuya Masu, Takumi Uezono, Takanori Kyogoku, Kenichi Okada

Publikováno v: Japanese Journal of Applied Physics. 45:2476-2480

The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of inte

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6e0a255e5784a85117af34efa0b4f91d
https://doi.org/10.1143/jjap.45.2476

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Wire Length Distribution Model for System LSI

Autor: Takanori Kyogoku, Kazuya Masu, Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Takumi Uezono

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3445-3452

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as pow

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2afae2606b9fce899e7dcb352a83998f
https://doi.org/10.1093/ietfec/e88-a.12.3445

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Evaluation of X Architecture Using Interconnect Length Distribution

Autor: Naohiro Takagi, Hidenari Nakashima, Kazuya Masu, Kenichi Okada, Junpei Inoue

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3437-3444

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45°-wire orientations in addition to 90°-wire orientations, which contributes to reduce the total wire length and the numbe

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1eb04fa1286f90616063a3c075db866b
https://doi.org/10.1093/ietfec/e88-a.12.3437

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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

Autor: Hidenari Nakashima, Kazuya Masu, Junpei Inoue, Kenichi Okada

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3358-3366

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been rep

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ee9a134a1cb62c38845b9b9e56b3583
https://doi.org/10.1093/ietfec/e88-a.12.3358

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Chip oriented target impedance for digital power distribution network design

Autor: Masahiro Toyama, Masahiro Haida, Hidenari Nakashima, Mikiko Sode Tanaka, Junichi Yamada, Izumi Ooshima

Publikováno v: 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

With the advancements in semiconductor process technologies in recent years, noise management has become more difficult. Therefore power distribution network (PDN) design has become more important. This paper describes the target impedance build meth

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8b0f81d02381789988ac27b31af078c0
https://doi.org/10.1109/epeps.2012.6457881

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