Zobrazeno 1 - 10
of 46
pro vyhledávání: '"Hidemi Ishiuchi"'
Autor:
Mark Neisser, Harry J. Levinson, Stefan Wurm, David Kyser, Takeo Watanabe, Ken Macwilliams, Hidemi Ishiuchi, Walt Trybula, Naoya Hayashi, Ted Fedynyshyn, Craig Higgins, Tsuyoshi Nakamura, Doug Resnick, Moshe Preil, Michael Lercel, Hajime Aoyama, Erik Hosler
Publikováno v:
2021 IEEE International Roadmap for Devices and Systems Outbriefs.
Autor:
Linda Wilson, Hidemi Ishiuchi, Paolo Gargini, Alan Allan, Francis Balestra, Yoshihiro Hayashi, Leo Kenny
Publikováno v:
2021 IEEE International Roadmap for Devices and Systems Outbriefs.
Autor:
A. Hokazono, Chenming Hu, Tiehui Liu, Sriram Balasubramanian, Kazunari Ishimaru, Hidemi Ishiuchi
Publikováno v:
IEEE Transactions on Electron Devices. 55:2657-2664
Forward body biasing is a promising approach for realizing optimum threshold-voltage (V TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSF
Autor:
Kazunari Ishimaru, Chenming Hu, Hidemi Ishiuchi, A. Hokazono, Tiehui Liu, Sriram Balasubramanian
Publikováno v:
IEEE Electron Device Letters. 27:605-608
Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impa
Autor:
Kiyotaka Miyano, Y. Tsunashima, Satoshi Inaba, Yoshiaki Toyoshima, Kazuya Ohuchi, Ichiro Mizushima, Hidemi Ishiuchi, Hisato Oyamatsu, Akira Hokazono, Kazunari Ishimaru, Hajime Nagano
Publikováno v:
IEEE Transactions on Electron Devices. 51:1401-1408
In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel regio
Autor:
Tatsuya Ohguro, Hiroshi Iwai, S. Nakamura, Hidemi Ishiuchi, Hisayo Momose, Yoshiaki Toyoshima
Publikováno v:
IEEE Transactions on Electron Devices. 49:1597-1605
The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time.
Autor:
Chenming Hu, A. Hokazono, Hidemi Ishiuchi, Sriram Balasubramanian, Tiehui Liu, Kazunari Ishimaru
Publikováno v:
IEEE Electron Device Letters. 27:387-389
Forward body biasing is a solution for continued scaling of bulk-Si CMOS technology. In this letter, the dependence of 30-nm-gate MOSFET performance on body bias is experimentally evaluated for devices with various channel-doping profiles to provide
Autor:
Kazuyoshi Muraoka, T. Kimura, Tohru Furuyama, S. Sugiura, Yohji Watanabe, Y. Kohyama, H. Tanaka, Hidemi Ishiuchi, K. Natori
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:42-47
A latch-up-like failure phenomenon that shows hysteresis in the V/sub cc/-I/sub cc/ characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-
Autor:
Sadayuki Yoshitomi, Hidemi Ishiuchi, Hisayo Momose, Yoshiaki Toyoshima, Tatsuya Ohguro, K. Kojima
Publikováno v:
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that o
Autor:
Hidemi Ishiuchi, Takahisa Kanemura, Yoshiaki Toyoshima, Takashi Izumida, K. Okano, T. Kubota, M. Omura, Kazuhiro Eguchi, A. Kinoshita, Kazunari Ishimaru, K. Yahashi, Satoshi Inaba, Nobutoshi Aoki, Ichiro Mizushima, Junji Koga, H. Kawasaki, Akio Kaneko, K. Suguro, K. Matsuo, Y. Tsunashima, Atsushi Yagishita
Publikováno v:
2006 International Electron Devices Meeting.
High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with Lg =