Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Hideki Naganuma"'
Autor:
Tetsu Tanaka, Takafumi Fukushima, Hideki Naganuma, Seiya Tanikawa, Kang-Wook Lee, Mariappan Murugesan, Jichoel Bea, Mitsumasa Koyanagi
Publikováno v:
IEEE Transactions on Electron Devices. 61:379-385
The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending
Autor:
Seiya Tanikawa, Hideki Naganuma, Tetsu Tanaka, Takafumi Fukushima, Haro Shimamoto, Kang-Wook Lee, Mitsumasa Koyanagi, M. Murugesan
Publikováno v:
IEEE Electron Device Letters. 34:1038-1040
The Young's modulus (E) of Si substrate begin to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice stru
Autor:
Takaharu Tani, Hideki Naganuma, Kang-Wook Lee, Mitsumasa Koyanagi, Takafumi Fukushima, Yoshikazu Ohara, Tetsu Tanaka
Publikováno v:
IEEE Electron Device Letters. 33:1297-1299
The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 °C
Autor:
Seiya Tanikawa, Hideki Naganuma, Takafumi Fukushima, M. Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi, Jichel Bea
Publikováno v:
2014 IEEE International Reliability Physics Symposium.
The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CM
Autor:
K-W Lee, M. Murugesan, Tetsu Tanaka, Hideki Naganuma, Mitsumasa Koyanagi, Takafumi Fukushima, Seiya Tanikawa, J-C Bea
Publikováno v:
3DIC
The Young's modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, t
Publikováno v:
Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials.
Publikováno v:
Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials.
Publikováno v:
Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials.
Autor:
Tetsu Tanaka, Hideki Naganuma, Takafumi Fukushima, Koji Kiyoyama, Mitsumasa Koyanagi, K. W. Lee, Harufumi Kobayashi
Publikováno v:
3DIC
This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked
Autor:
Tetsu Tanaka, Hideki Naganuma, Harufumi Kobayashi, Takafumi Fukushima, Mitsumasa Koyanagi, K-W Lee, K. Kiyoyama
Publikováno v:
3DIC
In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed imag