Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Hidekazu Kikuchi"'
Autor:
Toshio, Shimamura, Masaki, Izumo, Yukio, Sato, Noriko, Shiokawa, Nina, Uenomachi, Motoki, Miyauchi, Junko, Miyamoto, Hidekazu, Kikuchi, Junko, Shinoda, Takanori, Okamura, Yoshihiro J, Akashi
Publikováno v:
Echocardiography. 39:1338-1343
Although Doppler evaluation using a multiplanar method is recommended to assess the severity of aortic stenosis (AS) with transthoracic echocardiography, evidence on the diagnostic significance of a non-apical method is limited. This study aimed to c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::35c581a0a1b2c55b4f5860b946e66d87
https://doi.org/10.1111/echo.15464
https://doi.org/10.1111/echo.15464
Autor:
Shinya Miyata, Ryo Hayashibara, Masahiko Nakamizo, Tadayuki Taura, Keiji Tatani, Yusuke Oike, Hirotsugu Takahashi, Satoshi Yamamoto, Naoki Jyo, Yasuhisa Tochigi, Takayuki Ezaki, Takuya Wada, Masaki Sakakibara, Ogawa Koji, Hidekazu Kikuchi, Yoshiyuki Ota, Katsumi Honda, Tsukasa Miura, Yasunobu Kamikubo, Shin Sakai, Teruo Hirayama
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:3017-3025
In this paper, we report on a back-illuminated, global shutter, CMOS image sensor (CIS) with a pixel-parallel, single-slope analog-to-digital converter (ADC). We adopted a digital bucket relay transfer with multistage flip-flop connection, a pixel un
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f41365ebaedd007876cf3b3bc3a155d2
https://doi.org/10.1109/jssc.2018.2863947
https://doi.org/10.1109/jssc.2018.2863947
Autor:
Teruo Hirayama, Naoki Jyo, Tadayuki Taura, Yusuke Oike, Masahiko Nakamizo, Satoshi Yamamoto, Yasuhisa Tochigi, Yoshiyuki Ota, Ryo Hayashibara, Keiji Tatani, Ogawa Koji, Hirotsugu Takahashi, Katsumi Honda, Hidekazu Kikuchi, Shinya Miyata, Takayuki Ezaki, Takashi Nagano, Yasunobu Kamikubo, Shin Sakai, Takuya Wada, Yohei Furukawa, Tsukasa Miura, Masaki Sakakibara
Publikováno v:
ISSCC
Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless of the speed at which these sensors are operated. It has been reported that by adopting in-pixel ana
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4e153f6dd8663f43a449007a57dc870
https://doi.org/10.1109/isscc.2018.8310193
https://doi.org/10.1109/isscc.2018.8310193
Autor:
Masahiro Aoyagi, Naoya Watanabe, Haruo Shimamoto, Azusa Yanagisawa, Katsuya Kikuchi, Hidekazu Kikuchi, Akio Nakamura
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
To confirm the effectiveness of the via-last through silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer, we evaluated the metal contamination caused by this process. The metal contamination generate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ace8695f81319fb368bc1e86cb01f6ad
https://doi.org/10.1109/ectc.2017.144
https://doi.org/10.1109/ectc.2017.144
Autor:
Akio Nakamura, Katsuya Kikuchi, Naoya Watanabe, Hidekazu Kikuchi, Azusa Yanagisawa, Masahiro Aoyagi, Haruo Shimamoto
Publikováno v:
Japanese Journal of Applied Physics. 58:SDDL09
We combined a "via-last through-silicon via (TSV) process consisting of notchless Si etching and wet cleaning of the first metal layer" with the solder bonding process using Ar fast atom beam (FAB), and realized the fabrication and three-dimensional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0c2a84916dc3ccdfd46b5d84c4c4daf
https://doi.org/10.7567/1347-4065/ab088d
https://doi.org/10.7567/1347-4065/ab088d
Autor:
Hidekazu Kikuchi, Akio Nakamura, Katsuya Kikuchi, Azusa Yanagisawa, Masahiro Aoyagi, Naoya Watanabe, Haruo Shimamoto
Publikováno v:
3DIC
The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two problems: (1) the notching near the bottom corners of TSVs and (2) the reaction product generated b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db1126242e3bc0d229059fb8a7d5df24
https://doi.org/10.1109/3dic.2016.7970026
https://doi.org/10.1109/3dic.2016.7970026
Publikováno v:
Journal of Architecture and Planning (Transactions of AIJ). 73:1929-1937
This study indicates a state of recipient of the emergency medical care and intend to optimal location planning of facilities by constructing areal guidelines in emergency medical system.This paper aims at construction of areal planning method using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7110941edaf81b634c14dd74564560b4
https://doi.org/10.3130/aija.73.1929
https://doi.org/10.3130/aija.73.1929
Autor:
Azusa Yanagisawa, Akio Nakamura, Masahiro Aoyagi, Naoya Watanabe, Katsuya Kikuchi, Hidekazu Kikuchi, Haruo Shimamoto
Publikováno v:
Japanese Journal of Applied Physics. 56:07KE02
A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleanin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a863f4b520021c2c0448edbb9ac31faa
https://doi.org/10.7567/jjap.56.07ke02
https://doi.org/10.7567/jjap.56.07ke02
Autor:
Futoshi Furuta, Kazuyuki Hozawa, Kenichi Takeda, T. Mitsuhashi, Yuko Hanaoka, Hidekazu Kikuchi, A. Yanagisawa, Mayu Aoki
Publikováno v:
2013 IEEE International Electron Devices Meeting.
A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backside-via-last TSV (7-μm diameter/25-μm length) processes. Successful fabrication of this wafer confirmed that copper/polymer hybri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00a443e30fcaabdd766438b6f26613ca
https://doi.org/10.1109/iedm.2013.6724718
https://doi.org/10.1109/iedm.2013.6724718
Autor:
Katsuyuki Sakuma, Junichi Takamatsu, Keiji Matsumoto, Yasumitsu Orii, Soichiro Ibaraki, Kohei Fujihara, Koji Kondo, Kuniaki Sueoka, Hidekazu Kikuchi, Fumiaki Yamada, Hiroyuki Mori
Publikováno v:
3DIC
In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5439417faead1632099993d184dfa3f2
https://doi.org/10.1109/3dic.2013.6702329
https://doi.org/10.1109/3dic.2013.6702329