Výsledky vyhledávání - "Hidehiro Fujiwara"

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

Autor: Koji Nii, Yasumasa Tsukamoto, Miki Tanaka, Makoto Yabuuchi, Hidehiro Fujiwara, Shinji Shinji

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:2335-2344

We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to rea

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4a8adebbc3c4ce0b91736c30cb1a704b
https://doi.org/10.1109/tvlsi.2018.2864267

Zobrazit plný text záznamu

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Autor: Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu

Publikováno v: 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::767fe9e873b7144ea10dcc2b8bc11961
https://doi.org/10.1109/isscc.2017.7870333

Zobrazit plný text záznamu

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Autor: Yasumasa Tsukamoto, Koji Nii, Kazumasa Yanagisawa, Yuichiro Ishii, Hidehiro Fujiwara, Yuji Kihara, Shinji Tanaka

Publikováno v: IEEE Journal of Solid-State Circuits. 46:2535-2544

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operatio

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c2634b86cd28b5bd70d527813ffdc53b
https://doi.org/10.1109/jssc.2011.2164021

Zobrazit plný text záznamu

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential

Autor: Hiroshi Kawaguchi, Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Yusuke Iguchi, Masahiko Yoshimoto, Shunsuke Okumura

Publikováno v: IPSJ Transactions on System LSI Design Methodology. 4:80-90

As process technology is scaled down, a large-capacity SRAM will be used. Its power must be lowered. The Vth variation of the deep-submicron process affects the SRAM operation and its power. This paper compares the macro area, readout power, and oper

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d4a3096b9b067765627b6699e24edfc3
https://hdl.handle.net/20.500.14094/90002988

Zobrazit plný text záznamu

A Dependable SRAM with 7T/14T Memory Cells

Autor: Masahiko Yoshimoto, Hidehiro Fujiwara, Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hiroshi Kawaguchi

Publikováno v: IEICE Transactions on Electronics. :423-432

SUMMARY This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a normal mode, highspeed mode, and dependable mode, and dynamically sc

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::31a998c542d4c118e1a954ae75b7a305
https://doi.org/10.1587/transele.e92.c.423

Zobrazit plný text záznamu

A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing

Autor: Hiroki Noguchi, Yusuke Iguchi, Masahiko Yoshimoto, Hidehiro Fujiwara, Hiroshi Kawaguchi, Yasuhiro Morita, Shunsuke Okumura, Koji Nii

Publikováno v: IEICE Transactions on Electronics. :543-552

We propose a low-power non-precharge-type two-port SRAM for video processing that exploits statistical similarity in images. To minimize the charge/discharge power on a read bitline, the proposed memory cell (MC) has ten transistors (10T), comprised

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::30eb1f8efd0b088419bc197da2c5f67b
https://doi.org/10.1093/ietele/e91-c.4.543

Zobrazit plný text záznamu

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

Autor: Hiroshi Kawaguchi, Yasuhiro Morita, Hidehiro Fujiwara, Masahiko Yoshimoto, Koji Nii, Hiroki Noguchi, Yusuke Iguchi

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2695-2702

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::da5574e36cacd1cc2aff6c8ca6ecb241
https://doi.org/10.1093/ietfec/e90-a.12.2695

Zobrazit plný text záznamu

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Autor: Hiroshi Kawaguchi, Yasuhiro Morita, Junichi Miyakoshi, Shinji Mikami, Masahiko Yoshimoto, Hiroki Noguchi, Koji Nii, Hidehiro Fujiwara, Kentaro Kawakami

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3634-3641

元・大学院自然科学研究科
現・神戸大学大学院自然科学研究科
We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2c43898b018ada4073bf1e42ad1f43d7
https://doi.org/10.1093/ietfec/e89-a.12.3634

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání