Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Heung-Sup Chun"'
Publikováno v:
Journal of Electronic Materials. 29:1233-1240
Chip scale packages (CSP) have essential solder joint quality problems, and a board level reliability is a key issue in design and development of the CSP type packages. There has been an effort to eliminate Pb from solder due to its toxicology. To ev
Autor:
Hyo-Seog Ryu, Jo-Han Kim, Joong-Sik Ki, Young-Suk Suh, Yong-Ju Kim, Heung-Sup Chun, Jae-Kyung Wee
Publikováno v:
2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
In this paper, three s-parameter based techniques of meandering traces modeled on uniform transmission line model, optimized /spl Pi/-network model, and the Cauer network synthesis technique, are presented to obtain time-domain responses using time d
Publikováno v:
2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
Hyundai Electronics has developed the wafer level chip size package, named Omega CSP, to provide the right package solution for mobile electronics products that require light weight, small size and low cost. The aim of this paper is to report both th
Publikováno v:
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
Six types of under bump metallurgies (UBM) were investigated in terms of ball shear strength, fracture surface analysis, the adhesion of sputter-deposited metal to dielectric polymer, and microstructure observation to optimize the UBM of a wafer leve
Publikováno v:
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
CSP (Chip Size Package) is expected to be widely used in D-RDRAM (Direct Rambus DRAM) for its higher electrical performance as well as in PDA (Personal Digital Assistant) applications for its smaller size and lighter weight. Especially wafer level CS
Autor:
Seungyoung Ahn, Junwoo Lee, Kwang Seong Choi, Joon-Ki Hong, Woonghwan Ryu, Jae Myun Kim, Heung-Sup Chun, Baekkyu Choi, Joungho Kim
Publikováno v:
2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
A wafer level package (WLP) has been developed as a cost effective packaging method compared to the /spl mu/BGA package, and especially applied to the Rambus DRAM (RDRAM) package. The maximum allowable thickness of the stress buffer layer on the WLP
Autor:
Yong-Ju Kim, Jo-Han Kim, Hyo-Seog Ryu, Young-Suk Suh, Jae-Kyung Wee, Heung-Sup Chun, Joong-Sik Ki
Publikováno v:
2001 Proceedings 51st Electronic Components & Technology Conference (Cat. No.01CH37220); 2001, p1463-1467, 5p
Autor:
Junwoo Lee, Baekkyu Choi, Seungyoung Ahn, Woonghwan Ryu, Jae Myun Kim, Kwang Seong Choi, Joon-Ki Hong, Heung-Sup Chun, Joungho Kim
Publikováno v:
2001 Proceedings 51st Electronic Components & Technology Conference (Cat. No.01CH37220); 2001, p128-132, 5p
Publikováno v:
2000 Proceedings 50th Electronic Components & Technology Conference (Cat. No.00CH37070); 2000, p844-849, 6p
Publikováno v:
2000 Proceedings 50th Electronic Components & Technology Conference (Cat. No.00CH37070); 2000, p301-310, 10p