Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Herve Yviquel"'
Publikováno v:
2022 IEEE Workshop on Signal Processing Systems (SiPS)
2022 IEEE Workshop on Signal Processing Systems (SiPS), Nov 2022, Rennes, France
2022 IEEE Workshop on Signal Processing Systems (SiPS), Nov 2022, Rennes, France
International audience; Dataflow programming is considered a good solution for the implementation of parallel signal processing applications. However, the strict separation between kernel and coordination codes limits the variety of possible optimiza
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::206920b0e9cade7dcc780fadd81ea49a
https://hal.science/hal-03845902/file/dfmlir___SiPS22.pdf
https://hal.science/hal-03845902/file/dfmlir___SiPS22.pdf
Publikováno v:
2022 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW).
Autor:
Carla Cardoso, Herve Yviquel, Guilherme Valarini, Gustavo Leite, Rodrigo Ceccato, Marcio Pereira, Alan Souza, Guido Araujo
Publikováno v:
2022 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW).
Autor:
Samuel Cajahuaringa, Leandro N. Zanotto, Daniel L. Z. Caetano, Sandro Rigo, Herve Yviquel, Munir S. Skaf, Guido Araujo
Publikováno v:
2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
Autor:
Guilherme Valarini, Guido Araujo, Renan Sterle, Marcio Machado Pereira, Herve Yviquel, Ramon Nepomuceno
Publikováno v:
FCCM
FPGA-based hardware accelerators have received increasing attention mainly due to their ability to accelerate deep pipelined applications, thus resulting in higher computational performance and energy efficiency. Nevertheless, the amount of resources
Publikováno v:
SBAC-PAD
One of the greatest challenges of modern computing is the development of software for parallel execution. To address such challenge, programmers use profiling tools to record relevant operations, like the communications that the different parts of an
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 15:1-23
Computation offloading is a programming model in which program fragments (e.g., hot loops) are annotated so that their execution is performed in dedicated hardware or accelerator devices. Although offloading has been extensively used to move computat
Publikováno v:
SBAC-PAD
Rendering an image from a 3D scene requires a large amount of computation which grows exponentially with the complexity of the scene (e.g. number of objects and light sources). With the increasing demand of high definition content, 3D designers need
Autor:
Guido Araujo, Herve Yviquel
Publikováno v:
ICPP
Computation offloading is a programming model in which program fragments (e.g. hot loops) are annotated so that their execution is performed in dedicated hardware or accelerator devices. Although offloading has been extensively used to move computati
Autor:
Marco Mattavelli, Daniele Renzi, Khaled Jerbi, Damien De Saint Jorre, Claudio Alberti, Alexandre Sanchez, Herve Yviquel, Mickaël Raulet
Publikováno v:
Journal of Signal Processing Systems
Journal of Signal Processing Systems, 2017, 87 (1), pp.127-138. ⟨10.1007/s11265-016-1113-x⟩
Journal of Signal Processing Systems, Springer, 2017, 87 (1), pp.127-138. ⟨10.1007/s11265-016-1113-x⟩
Journal of Signal Processing Systems, 2017, 87 (1), pp.127-138. ⟨10.1007/s11265-016-1113-x⟩
Journal of Signal Processing Systems, Springer, 2017, 87 (1), pp.127-138. ⟨10.1007/s11265-016-1113-x⟩
International audience; With the emergence of the High Efficiency Video Coding (HEVC) standard, a dataflow description of the decoder part was developed as part of the MPEG-B standard. This dataflow description presented modest framerate results whic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dee2e490d54cbf45649e521c84239817
https://hal.science/hal-01298595/document
https://hal.science/hal-01298595/document