A Markov chain based method for NoC end-to-end latency evaluation.

Autor: Foroutan, S., Thonnart, Y., Hersemeule, R., Jerraya, A.

Publikováno v: 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops & Phd Forum (IPDPSW); 2010, p1-8, 8p

LOTOS code generation for model checking of STBus based SoC: the STBus interconnection.

Autor: Wodey, P., Camarroque, G., Baray, F., Hersemeule, R., Cousin, J.-P.

Publikováno v: Proceedings of the First ACM & IEEE International Conference on Formal Methods & Models for Co-Design, 2003. MEMOCODE '03; 2003, p204-213, 10p

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures.

Autor: Coste, N., Hermanns, H., Thonnart, Y., Garavel, H., Hersemeule, R., Zidouni, M.

Publikováno v: 2008 Design, Automation & Test in Europe; 2008, p88-89, 2p