A Markov chain based method for NoC end-to-end latency evaluation.

Autor: Foroutan, S., Thonnart, Y., Hersemeule, R., Jerraya, A.

Publikováno v: 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops & Phd Forum (IPDPSW); 2010, p1-8, 8p

LOTOS code generation for model checking of STBus based SoC: the STBus interconnection.

Autor: Wodey, P., Camarroque, G., Baray, F., Hersemeule, R., Cousin, J.-P.

Publikováno v: Proceedings of the First ACM & IEEE International Conference on Formal Methods & Models for Co-Design, 2003. MEMOCODE '03; 2003, p204-213, 10p

Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures.

Autor: Coste, N., Hermanns, H., Thonnart, Y., Garavel, H., Hersemeule, R., Zidouni, M.

Publikováno v: 2008 Design, Automation & Test in Europe; 2008, p88-89, 2p

Optimal low-latency network topologies for cluster performance enhancement.

Autor: Deng, Yuefan, Guo, Meng, Ramos, Alexandre F., Huang, Xiaolong, Xu, Zhipeng, Liu, Weifeng

Publikováno v: Journal of Supercomputing; Dec2020, Vol. 76 Issue 12, p9558-9584, 27p

Smart Reduction.

Autor: Crouzen, Pepijn, Lang, Frédéric

Publikováno v: Fundamental Approaches to Software Engineering: 14th International Conference, FASE 2011, Held as Part of the Joint European Conferences on Theory & Practice of Software, ETAPS 2011, Saarbrücken, Germany, March 26-April 3, 2011. Proceedings; 2011, p111-126, 16p