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Case study: deployment of the 2D NoC on 3D for the generation of large emulation platforms

Autor: Junyan Tan, Virginie Fresse, Zhiwei Ge, Frederic Rousseau

Publikováno v: IEEE International Symposium on Rapid System Prototyping
IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland. 7 p
RSP
IPTA

International audience; The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced explora

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d90be9e91ca9611e45ef58fafb976a91
https://hal-ujm.archives-ouvertes.fr/ujm-00738489

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Dynamically Scalable NoC Architecture for Implementing Run-Time Reconfigurable Applications.

Autor: Ijaz, Qaiser, Kidane, Hiliwi Leake, Bourennane, El-Bay, Ochoa-Ruiz, Gilberto

Publikováno v: Micromachines; Oct2023, Vol. 14 Issue 10, p1913, 14p

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip.

Autor: Zhang, Ying, Ji, Peng-Fei, Zhu, Pan-Wei, Peng, Zebo, Li, Hua-Wei, Jiang, Jian-Hui

Publikováno v: Journal of Computer Science & Technology (10009000); Apr2023, Vol. 38 Issue 2, p405-421, 17p