Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Hema Ramamurthy"'
Autor:
Tom Herrmann, Hongsik Yoon, Torsten Klick, Alban Zaka, Seunghwan Seo, Juergen Faul, Joerg Schmid, J. Kluth, Sandra Hecker, Zhen Xu, Udo Ziller, Chang Ming-Cheng, Ralf vanBentum, Gabriele Congedo, Vivek Joshi, Xin Zou, Hema Ramamurthy, Nigel Chan, Elke Erben, Youmean Lee, Petra Poth, C. Weintraub, Gerd Zschaetzsch
Publikováno v:
ESSDERC
This paper presents a 0.110um2Ultra Low Leakage (ULL) 6T-SRAM for Internet Of Things (lOT) application with competitive 0.7pA/cell retention leakage and $\pmb{1.45}\mathbf{mV}^{\ast}\mathbf{um}$ transistor mismatch coefficient (AVT). A back gate dopi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e38aac1663ffb60b67b2bc0350072117
https://doi.org/10.1109/essderc.2018.8486897
https://doi.org/10.1109/essderc.2018.8486897
Publikováno v:
ICICDT
The utilization of FinFET devices in the SRAM cell provides many benefits over planar bulk devices due to the fully-depleted behavior with improved subthreshold slope, short-channel effects, drive current, and mismatch. However, the quantized nature
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::499485d68bdd67d892a7377358a10fcc
https://doi.org/10.1109/icicdt.2014.6838606
https://doi.org/10.1109/icicdt.2014.6838606
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540200741
PATMOS
PATMOS
Reducing the ever-growing leakage current is critical to high performance and power efficient designs. We present an in-depth study of high-level leakage modeling and reduction in the context of a full custom design environment. We propose a methodol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b4b0aa567c8956d666f3544832a43f3
https://doi.org/10.1007/978-3-540-39762-5_32
https://doi.org/10.1007/978-3-540-39762-5_32
Publikováno v:
ITC
This paper presents a new method for detecting defect and fabrication variations in both digital and analog CMOS circuits by simultaneously pulsing the power supply rails and analyzing the temporal and/or the spectral characteristics of the resulting
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::864270f435743b6965691c1587aec7ca
https://doi.org/10.1109/test.1993.470641
https://doi.org/10.1109/test.1993.470641
Publikováno v:
IEE Proceedings - Computers and Digital Techniques. 152:747
The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via power-gating is effective to reduce leakage power, but it introduces power-up cur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2207f8dc79e459e0ed10d131f9a3ee5
https://doi.org/10.1049/ip-cdt:20045165
https://doi.org/10.1049/ip-cdt:20045165
Publikováno v:
Electronics Letters. 29:2101
A test method is presented for detecting defects and fabrication variations in both digital and analogue circuits by simultaneously pulsing the power supply rails and analysing the temporal and/or the spectral characteristics of the resulting transie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::538930aac48c0fd203f01f8fbdeec7ac
https://doi.org/10.1049/el:19931405
https://doi.org/10.1049/el:19931405
Autor:
Vivek Joshi, Elliot John Smith, Jürgen Faul, Torsten Klick, C. Weintraub, Joerg Schmid, X. Zou, Seunghwan Seo, R. vanBentum, Sriram Balasubramanian, Hema Ramamurthy, J. Yun, Nigel Chan, Hongsik Yoon
Publikováno v:
2017 Symposium on VLSI Technology
We present the SRAM bitcell offering from 22FDXTM (a 22nm FDSOI technology) with competitive 1.46mV-µm FinFET-like transistor mismatch coefficient (AVt) built with low cost planar architecture. Extremely low minimum operating voltages (V min ) are r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3209e125d6c7ee5d26075a7d75e3da76