Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Helmut Bierstedt"'
Autor:
Helmut Bierstedt, Manfred Horstmann, Mark Kennard, Klaus Hempel, Anthony Mowry, Ralf Otterbach, Thorsten Kammler, Ian Cayrefourcq, Jochen Rinderknecht, Bernhard Trui, A. Hellmich, J. Hontschel, Andy Wei, Eric Guiot, F. Metral
Publikováno v:
ECS Transactions. 3:719-725
Embedded-SiGe is shown to be fully compatible with strained-SOI substrates. Despite a lack of lateral lattice mismatch between the SiGe and strained-SOI, the resulting drive current improvement from embedded-SiGe is identical for strained-SOI and sta
Autor:
Ina Ostermay, Anthony Mowry, Thorsten Kammler, Peter Kücher, Johann W. Bartha, Kornelia Dittmar, Helmut Bierstedt, Bernhard Trui, Andreas Naumann, Stephan Kronholz
Publikováno v:
Materials Science and Engineering: B. :95-97
An advanced CMOS scheme for the integration of a graded epitaxial Silicon Germanium (SiGe) layer is presented. SiGe is deposited into the source drain regions right after gate formation to create compressive strain in the transistor channel of the pM
Autor:
John A. Fitzsimmons, Vincent J. McGahay, K. Malone, M. Minami, Siddhartha Panda, Manfred Horstmann, A. Wei, Helmut Bierstedt, H. Nii, A. Waite, A. Sakamoto, Michael A. Gribelyuk, M. Cullinan-Scholl, D. Harmon, A. Hellmich, M. Kiene, Patrick Press, Hartmut Ruelke, H. Zhu, H. Chen, H. Nakayama, Anthony G. Domenicucci, G. Sudo, Henry A. Nye, P. Fisher, Hans-Jürgen Engelmann, H. VanMeer, M. Newport, X. Chen, Tenko Yamashita, Cathryn Christiansen, Hasan M. Nayfeh, Dureseti Chidambarrao, Guido Koerner, Christopher D. Muzzy, S.-F. Huang, Ralf Otterbach, David M. Fried, J. Kluth, Jörg Hohage, M. Trentsch, I. Peidous, Thorsten Kammler, Mukesh Khare, Dominic J. Schepis, K. Rim, Spooner Terry A, K. Miyamoto, P.V. McLaughlin, Michael Raab, T. H. Ivers, Dan Mocuta, D.R. Davies, Jason Gill, Scott Luning, Woo-Hyeong Lee, Gary B. Bronner, Judson R. Holt, Gregory G. Freeman, Matthias Schaller, R. Murphy, J. Pellerin, J. Klais, Kai Frohberg, A. Neu, N. Kepler, R. Bolam, C. Labelle, Anuj Madan, K. Hempel, C. Reichel, Heike Salz, J. Hontschel, T. Sato, J. Cheng, D. Greenlaw, Linda Black, Paul D. Agnello, K. Ida
Publikováno v:
Scopus-Elsevier
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a n
Autor:
A. Hellmich, S. Weiher-Telford, C. Ziemer-Popp, Th. Feudel, H.-J. Engelmann, Guido Koerner, A. Wei, Rolf Stephan, O. Herzog, K. Hempel, Jens-Peter Biethan, C. Reichel, J. Hontschel, Helmut Bierstedt, Peter Javorka, A. Neu, J. Klais, E. Sanchez, T. Mantei, M. Horstmann, D. Greenlaw, O. Luckner, P.-O. Hansson, N. Kepler, Michael Raab, Markus Lenski, Bernhard Trui, A. Samoilov, Christoph Schwan, Ralf Otterbach, Thorsten Kammler, Gert Burbach
Publikováno v:
Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials.
Autor:
Guido Koerner, Hans-Jürgen Engelmann, H. Nii, Martin Gerhardt, Andy Wei, Hartmut Ruelke, L. T. Su, Mukesh Khare, Manfred Horstmann, Rolf Stephan, O. Herzog, Ralf Otterbach, Judson R. Holt, Dureseti Chidambarrao, Peter Javorka, Helmut Bierstedt, C. Reichel, P. Hubler, Heike Salz, J. Hontschel, H. Chen, Thorsten Kammler, Dominic J. Schepis, A. Hellmich, T. Sato, Woo-Hyeong Lee, N. Kepler, S. Liming, David M. Fried, Matthias Schaller, Michael Raab, Thomas Feudel, D. Greenlaw, Shih-Fen Huang, John Pellerin, Kai Frohberg, A. Neu, Patrick Press, J. Klais, Siddhartha Panda, Andrew Waite, K. Hempel, Markus Lenski, Bernhard Trui, Jörg Hohage, K. Rim, M. Trentsch
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization pro