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pro vyhledávání: '"Hejdström, Christoffer"'
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Hejdström, Christoffer
Manually designing hardware for fpga implementations is time consuming. Onepossible way to accelerate the development of hardware is to use high level syn-thesis (hls) tools. Such tools synthesizes a high level model written in a languagesuch as c++
Externí odkaz:
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-189401
