Zobrazeno 1 - 10
of 64
pro vyhledávání: '"Heiko Ehrenberg"'
Publikováno v:
2019 IEEE AUTOTESTCON.
Access to internal circuit nodes and elements from the system level improves test and diagnostic coverage. The traditional approach of tearing down a system in order to ascertain whether a subsystem, a circuit board or a component is in fact faulty i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16fbbcd4dda1191d7259a6bd3396fd51
https://doi.org/10.1109/autotestcon43700.2019.8961045
https://doi.org/10.1109/autotestcon43700.2019.8961045
Autor:
Sergei Odintsov, Thomas Wenzel, Artur Jutman, Igor Aleksejev, Sergei Devadze, Heiko Ehrenberg
Publikováno v:
2019 IEEE AUTOTESTCON.
With continually growing adoption of FPGA based designs, and more features and capabilities available in FPGAs, board and system level test applications can - and should - take advantage of FPGA embedded instrumentation. Such FPGA assisted tests not
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b66114e0694dbed3754f167a7eed5c1e
https://doi.org/10.1109/autotestcon43700.2019.8961057
https://doi.org/10.1109/autotestcon43700.2019.8961057
Autor:
Heiko Ehrenberg, Bob Russell
Publikováno v:
ITC
Memory devices have been becoming more complex with every generation and this trend is very likely to continue. Different kinds of memories present different challenges for board level test applications. In this paper we discuss several of those chal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dfd058078cc91deaa0ceb9b82c86747c
https://doi.org/10.1109/test.2011.6139141
https://doi.org/10.1109/test.2011.6139141
Autor:
Heiko Ehrenberg
Publikováno v:
ITC
IEEE P1581 is aimed at ICs that are otherwise not provisioned with Design For Test (DFT) for any reason, targeting primarily memory devices, but also allowing for implementation in other devices. This Poster provides an overview of Test Mode Entry an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84a298fa199c6cf5d1ca5d268b6f841d
https://doi.org/10.1109/test.2009.5355636
https://doi.org/10.1109/test.2009.5355636
Publikováno v:
ITC
IEEE P1581 has undergone significant improvement since its introduction. This paper explains the choice of simple, low overhead solutions the proposed standard provides in overcoming one of Boundary Scan's greatest bottlenecks: test of complex memory
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9ecebec9f79634709d14be3141f8854
https://doi.org/10.1109/test.2006.297707
https://doi.org/10.1109/test.2006.297707
Autor:
Heiko Ehrenberg, Thomas Wenzel
Publikováno v:
2006 IEEE Autotestcon.
JTAG/Boundary Scan tools for LXI1 allow a powerful and flexible combination with other test methodologies. This paper shortly discusses benefits and shortcomings of JTAG/Boundary Scan and Functional Test and then outlines possibilities of integrating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dabda037d4f94ebbb961df614ff04873
https://doi.org/10.1109/autest.2006.283765
https://doi.org/10.1109/autest.2006.283765
Publikováno v:
2006 IEEE International Test Conference; 2006, p1-9, 9p
Autor:
Ehrenberg, Heiko1, Wenzel, Thomas1
Publikováno v:
Electronics Weekly. 9/23/2009, Issue 2399, p16-16. 1p. 1 Diagram, 2 Charts.
Autor:
Wenzel, Thomas1 t.wenzel@goepel.com, Türk, Andreas1 a.tuerk@goepel.com
Publikováno v:
SMT: Surface Mount Technology. Jun2014, Vol. 29 Issue 6, p58-72. 11p.