Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Hegong Wei"'
Publikováno v:
IEEE Access, Vol 8, Pp 138944-138954 (2020)
This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to o
Externí odkaz:
https://doaj.org/article/72be75735ac94c9f94b938860f52ea4d
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:693-705
This article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::893035a487f6e48be41b4f2b010b9dd2
https://doi.org/10.1109/jssc.2019.2945298
https://doi.org/10.1109/jssc.2019.2945298
Publikováno v:
IEEE Access, Vol 8, Pp 138944-138954 (2020)
This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::184fda3ffe7dd9512fd112e161a3f5cb
https://doi.org/10.1109/access.2020.3012699
https://doi.org/10.1109/access.2020.3012699
Publikováno v:
VLSI Circuits
This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. We implement the sub-channel SAR with a splittin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c87546e8350f11a70cabc0d7f0ada5a
https://doi.org/10.23919/vlsic.2019.8778077
https://doi.org/10.23919/vlsic.2019.8778077
Publikováno v:
CICC
This paper presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background mismatch calibration. Benefitting from the proposed split TI topology, the mismatch calibration conver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0888e3f4a87becd9d96e215a97d2e1e
https://doi.org/10.1109/cicc.2019.8780222
https://doi.org/10.1109/cicc.2019.8780222
Publikováno v:
2011 IEEE 54th International Midwest Symposium on Circuits & Systems (MWSCAS); 2011, p1-4, 4p
Publikováno v:
2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2011, p188-190, 3p