Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Heejun Shim"'
Autor:
Chong-Min Kyung, Heejun Shim
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 19:1044-1050
In motion estimation for video codec, reducing the amount of external memory access is critical to reduce power consumption and to minimize performance degradation. Previous search area reuse algorithms to reduce the memory access still suffer from c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::932f4154c9c95c486092ea7b19172a2b
https://doi.org/10.1109/tcsvt.2009.2022704
https://doi.org/10.1109/tcsvt.2009.2022704
Autor:
Heejun Shim, Soojung Ryu
Publikováno v:
ISCAS
In a coarse-grained reconfigurable array (CGRA) architecture, software pipelining is primarily used to improve performance by exploiting loop-level parallelism (LLP). In this technique, the loop-carried memory dependence in user code prevents high pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93f6945d5b2fc7c9f47d49ba38daafef
https://doi.org/10.1109/iscas.2014.6865365
https://doi.org/10.1109/iscas.2014.6865365
Publikováno v:
MTV
We present verification and debugging of highly optimized executable code that is generated from C source code to run on CGRA (Coarse-Grained Reconfigurable Array). To generate the executable code, the CGRA compiler uses software pipelining technique
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::588420967c8c03e7ad5273f499fc73c2
https://doi.org/10.1109/mtv.2012.18
https://doi.org/10.1109/mtv.2012.18
Publikováno v:
VLSI-SoC
In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf pro- cessor using IPI(Inter-Prefetch Interval) energy model. In our previous work[1], we proposed a new energy estimation method, and pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::367c21fd247ae1b118c0bc2fa2b10115
https://doi.org/10.1109/vlsisoc.2007.4402502
https://doi.org/10.1109/vlsisoc.2007.4402502
Publikováno v:
ICME
Motion estimation has been widely studied and used to improve coding efficiency with small data access for power-saving. Conventional search area reuse algorithm requires small memory access by reuse of search area, but, suffers from coding efficienc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e4cf769d82f9872fa57287871fa863d
https://doi.org/10.1109/icme.2007.4284974
https://doi.org/10.1109/icme.2007.4284974
Publikováno v:
ACM Great Lakes Symposium on VLSI
This paper addresses a problem of modeling the power consumption of advanced off-the-shelf processors. Unlike existing methods for processor power estimation, where the internal information of processor architecture such as activation of specfic modu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5165e2a4eb426953ad8cbc7ece0699dd
https://doi.org/10.1145/1228784.1228923
https://doi.org/10.1145/1228784.1228923
Publikováno v:
IEEE International Workshop on Rapid System Prototyping
This paper presents fast co-simulation techniques aimed at multiprocessor-based system-on-chip (SoC) design. Unlike existing co-simulation tools that use a centralized server, which manages clocks for all processor models and inter-processor communic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cb5018236c7ee8eb08cc5537b7193af
https://doi.org/10.1109/rsp.2005.38
https://doi.org/10.1109/rsp.2005.38
Publikováno v:
2006 International Symposium on VLSI Design, Automation and Test.
This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7cc130634620aa35465b1a2930691d0
https://doi.org/10.1109/vdat.2006.258143
https://doi.org/10.1109/vdat.2006.258143
Automatic generation of software/hardware co-emulation interface for transaction-level communication
Autor:
Ki-Yong Aim, Young-Su Kwon, Wooseung Yang, Chong-Min Kyung, Heejun Shim, Young-Jin Kim, Ando Ki
Publikováno v:
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..
This paper presents a methodology for generating interface of a co-emulation system where processor and emulator execute testbench and design unit, respectively while interacting with each other. To reduce the communication time between the processor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83ceea71e54799be0ef932e51c36cde6
https://doi.org/10.1109/vdat.2005.1500054
https://doi.org/10.1109/vdat.2005.1500054
Publikováno v:
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.
In this paper we present a new RTL debugging methodology in FPGA-based verification platform. This method provides internal node probing in the co-simulation environment. Full observability is guaranteed using 32-bit scan module generated automatical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a836aec58f3a68d7d7cfa780bcf24abc
https://doi.org/10.1109/apasic.2004.1349442
https://doi.org/10.1109/apasic.2004.1349442