Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Hee Kong Phoon"'
Autor:
Wei-Yee Koay, Ty Garibay, Han Wooi Lim, Ron Ho, Andy Tong, Darren Faulkner, David Lewis, David Greenhill, Dana How, Herman Schmit, Peter McElheny, George Chen, Gopal Iyer, Duwel Keith, Jeffrey Erik Schulz, Atsatt Sean R, Hee Kong Phoon, Kok Hong Chan
Publikováno v:
ISSCC
A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceiv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76ed4121fcf1fd8c4e17fa2811f98989
https://doi.org/10.1109/isscc.2017.7870257
https://doi.org/10.1109/isscc.2017.7870257
Publikováno v:
2008 IEEE International Conference on Semiconductor Electronics.
Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b3cdd58d4c54f772576302d720e4602
https://doi.org/10.1109/smelec.2008.4770270
https://doi.org/10.1109/smelec.2008.4770270
Publikováno v:
2006 IEEE International Conference on Semiconductor Electronics.
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::652f0c6cfd07fb2662eb7812471edda6
https://doi.org/10.1109/smelec.2006.381114
https://doi.org/10.1109/smelec.2006.381114
Autor:
Michael D. Hutton, Sammy Cheung, Hee Kong Phoon, Jay Schleicher, Richard Yuan, Gregg William Baeckler, Kar Keng Chua
Publikováno v:
DATE Designers' Forum
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verifica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acbe8bca991d074a356cbfee4d4e18fa
https://doi.org/10.1109/date.2006.243775
https://doi.org/10.1109/date.2006.243775
Publikováno v:
2008 IEEE International Conference on Semiconductor Electronics; 2008, p27-32, 6p
Autor:
Hutton, M., Yuan, R., Schleicher, J., Baeckler, G., Cheung, S., Kar Keng Chua, Hee Kong Phoon
Publikováno v:
Proceedings of the Design Automation & Test in Europe Conference; 2006, p1-6, 6p