Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Hazar Yueksel"'
Autor:
P. A. Francese, Cosimo Aprile, Thomas Morf, Yusuf Leblebici, Hazar Yueksel, Gain Kim, Danny Luu, Christian Menolfi, Lukas Kull, Thomas Toifl, Andreas Burg, Alessandro Cevrero, Ilter Ozkaya, Matthias Braendli, Marcel Kossel
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:38-48
This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically pl
Autor:
Christian Menolfi, Thomas Morf, Danny Luu, Thomas Toifl, Lukas Kull, Qiuting Huang, Pier Andrea Francese, Hazar Yueksel, Matthias Brandli, Marcel Kossel, Ilter Ozkaya, Alessandro Cevrero
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:3268-3279
A single-channel 12-bit SAR ADC achieving 250–340 MS/s and consuming 4.8–8.0 mW from 0.75 to 0.9 V is presented. At 300 MS/s, the ADC exhibits 61.6-dB peak SNDR and reaches 60.5-dB SNDR and 78.7-dB SFDR with 0.8- $\text{V}_{\text {pp, diff}}$ inp
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
Autor:
Thomas Morf, Roy D. Cideciyan, Simeon Furrer, Marcel Kossel, Pier Andrea Francese, Hazar Yueksel, Giovanni Cherubini, Matthias Braendli, Lukas Kull, Danny Luu, Thomas Toifl, Andreas Burg, Christian Menolfi
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:3529-3542
The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105mW at a supply voltage of 0.7 V, corresponding to an energy efficien
Autor:
Christian Menolfi, Thomas Morf, Cosimo Aprile, Yusuf Leblebici, P. A. Francese, Marcel Kossel, Hazar Yueksel, Gain Kim, Matthias Braendli, Hyeon-Min Bae, Ilter Ozkaya, Lukas Kull, Thomas Toifl, Alessandro Cevrero, Andreas Burg, Danny Luu
Publikováno v:
A-SSCC
This work presents an ADC-based receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols are protected from the channel delay spread by the CP taps.
Autor:
Yusuf Leblebici, Matthias Braendli, Marcel Kossel, Alessandro Cevrero, Thomas Toifl, Danny Luu, Ilter Ozkaya, Lukas Kull, P. A. Francese, Cosimo Aprile, Hazar Yueksel, Andreas Burg, Christian Menolfi, Gain Kim, Thomas Morf
Publikováno v:
ISSCC
The increasing demand on bandwidth for communicating among processors through wired interconnects in large-scale servers motivates the increase in the lane-data-rate from the current 28Gb/s to 56Gb/s or further. Recently published works [1]–[3] dem
Autor:
Thomas Toifl, Hazar Yueksel, Lukas Kull, Danny Luu, Christian Menolfi, Marcel Kossel, Alessandro Cevrero, Ilter Ozkaya, Pier Andrea Francese, Matthias Brandli, Thomas Morf
Publikováno v:
ESSCIRC
A DDR4 transmitter (TX) for direct-attach memory on a processor chip is presented as well as the design of the associated low-dropout linear voltage regulators (LDO) that generate the split-mode supply voltages for the thin-oxide protection of the TX
Autor:
Thomas Morf, Marcel Kossel, Pier Andrea Francese, Ilter Ozkaya, Danny Luu, Lukas Kull, Qiuting Huang, Thomas Toifl, Hazar Yueksel, Matthias Braendli, Alessandro Cevrero, Christian Menolfi
Publikováno v:
ESSCIRC
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below
Autor:
Danny Luu, Thomas Toifl, Thomas Morf, Matthias Braendli, Lukas Kull, Qiuting Huang, Ilter Ozkaya, Hazar Yueksel, Marcel Kossel, Christian Menolfi, Alessandro Cevrero, Pier Andrea Francese
Publikováno v:
2017 Symposium on VLSI Circuits.
A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8V pp , diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regul
Autor:
Elisa Sacco, Christian Menolfi, Alessandro Cevrero, Thomas Morf, Georges Gielen, Matthias Brandli, Marcel Kossel, Hazar Yueksel, Danny Luu, Thomas Toifl, Pier Andrea Francese, Ilter Ozkaya, Lukas Kull
Publikováno v:
2017 Symposium on VLSI Circuits.
© 2017 JSAP. We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a f
Autor:
Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Hazar Yueksel, Marcel Kossel, Danny Luu, Alessandro Cevrero, Lukas Kull, Thomas Toifl, Thomas Morf, Ilter Ozkaya
Publikováno v:
ISSCC
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings