Zobrazeno 1 - 10
of 63
pro vyhledávání: '"Hasnain Lakdawala"'
Autor:
Sitaraman V. Iyer, Hasnain Lakdawala
Publikováno v:
Circuits at the Nanoscale ISBN: 9781315218762
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e86b06103a8d3fbccad04afffe442096
https://doi.org/10.1201/9781315218762-28
https://doi.org/10.1201/9781315218762-28
Autor:
Sandipan Kundu, Byunghoo Jung, Julia Hsin-Lin Lu, Jeyanandh Paramesh, Sarit Zur, Hasnain Lakdawala, Erkan Alpman, Eshel Gordon
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1929-1939
A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets $WiGig$ standard requirements with only background offset and gain calibrations. Sk
Autor:
Jonathan L. Holland, Stephen Knol, Li Sun, Sam Yang, Hai Dang, John Jianhong Zhu, Bo Yu, Reza Jalilizeinali, Xiaohua Kong, Chiew-Guan Tan, Alvin Leng Sun Loke, Lixin Ge, Tin Tin Wee, Zhiqin Chen, Da Yang, Kumar Albert, Kern Rim, Jun Yuan, Burton M. Leary, Wilson Jianbo Chen, Sreeker Dundigal, Deqiang Song, Chulkyu Lee, Steven James Dillen, Patrick G. Drennan, Esin Terzioglu, Stanley Seungchul Song, Hasnain Lakdawala, Periannan Chidambaram, Jihong Choi
Publikováno v:
Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design ISBN: 9783319612843
Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f9a93acedd44b3f7899ad05e8d60143
https://doi.org/10.1007/978-3-319-61285-0_14
https://doi.org/10.1007/978-3-319-61285-0_14
Autor:
Jorge Hermosillo, E. Borrayo, A. Del Rio, M. E. Guzman, A. Veloz, D. Arditti, Marian Verhelst, Hasnain Lakdawala, J. Carballido
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1669-1679
This paper presents a flexible and portable digital framework for Built-in Self-Test (BIST) and calibration of RF/analog circuitry. Novel to the proposed testing framework, is a reusable, flexible, drop-in IP core, composed of a centralized custom pr
Autor:
R. Yavatkar, Chang-Tsung Fu, Taehwan Kim, Hasnain Lakdawala, Ajay Balankutty, Chun Lee, Satoshi Suzuki, Hyung-Jin Lee, Rahul Limaye, P. Vandervoorn, Brent Carlton, Erkan Alpman, S. Ramamurthy, Jad B. Rizk, Durgesh Srivastava, Krishnamurthy Soumyanath, Duster Jon Sweat, Stefano Pellerano, Tan Yulin, C.-H. Jan, Marian Verhelst, Mark A. Schaecher, Ashoke Ravi, Satish Venkatesan, Khoa Minh Nguyen, Hyung Seok Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:91-103
An t 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulato
Autor:
Ashoke Ravi, Yorgos Palaskas, J. E. Zarate-Roldan, Paolo Madoglio, Kailash Chandrashekar, Hasnain Lakdawala, Stefano Pellerano, Masoud Sajadieh, O. Bochobza-Degani, Hongtao Xu, Luis Cuellar, Marian Verhelst, M. Aguirre-Hernandez
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:3184-3196
A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a re
Autor:
L.R. Carley, O. Bochobza-Degani, Wei Tai, Hasnain Lakdawala, Hongtao Xu, Ashoke Ravi, Yorgos Palaskas
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:1646-1658
A transformer-combined fully integrated outphasing class-D PA in 45 nm LP CMOS achieves 31.5 dBm peak output power at 2.4 GHz with 27% peak PAE, and supports over 86 dB of output power range. The PA employs dynamic power control (DPC) whereby section
Autor:
David J. Allstot, Daibashish Gangopadhyay, Subhanshu Gupta, Jacques C. Rudell, Hasnain Lakdawala
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:1141-1153
A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in b
Publikováno v:
Analog Integrated Circuits and Signal Processing. 65:197-208
Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, a
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:3621-3630
Monitoring temperature in a microprocessor is important for optimal energy consumption under various workloads. This paper presents a temperature sensor in a 32 nm high-k metal gate digital CMOS process for integration in a microprocessor core. The s