Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Harry Wagstaff"'
Publikováno v:
Spink, T, Wagstaff, H & Franke, B 2019, A Retargetable System-Level DBT Hypervisor . in Proceedings of the 2019 USENIX Annual Technical Conference . Renton, WA, pp. 505-520, 2019 USENIX Annual Technical Conference, Renton, United States, 10/07/19 . < https://www.usenix.org/conference/atc19/presentation/spink >
University of Edinburgh-PURE
Spink, T, Wagstaff, H & Franke, B 2020, ' A Retargetable System-Level DBT Hypervisor ', ACM Transactions on Computer Systems, vol. 36, no. 4, 14 . https://doi.org/10.1145/3386161
University of St Andrews CRIS
University of Edinburgh-PURE
Spink, T, Wagstaff, H & Franke, B 2020, ' A Retargetable System-Level DBT Hypervisor ', ACM Transactions on Computer Systems, vol. 36, no. 4, 14 . https://doi.org/10.1145/3386161
University of St Andrews CRIS
System-level Dynamic Binary Translation (DBT) provides the capability to boot an Operating System (OS) and execute programs compiled for an Instruction Set Architecture (ISA) different from that of the host machine. Due to their performance-critical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8c2cd8da6576f74a9c20ce744b497597
https://www.pure.ed.ac.uk/ws/files/93292802/A_Retargetable_System_retargetable_dbt_SPINK_DoA170419_AFV.pdf
https://www.pure.ed.ac.uk/ws/files/93292802/A_Retargetable_System_retargetable_dbt_SPINK_DoA170419_AFV.pdf
Autor:
Björn Franke, Michael O'Boyle, Bruno Bodin, Henrik Uhrenholt, Kuba Kaszyk, Tom Spink, Harry Wagstaff
Publikováno v:
ISPASS
Kaszyk, J, Wagstaff, H, Spink, T, Franke, B, O'Boyle, M, Bodin, B & Uhrenholt, H 2019, Full-System Simulation of Mobile CPU/GPU Platforms . in Proceedings of the International Symposium on Performance Analysis of Systems and Software 2019 (ISPASS 2019) . Institute of Electrical and Electronics Engineers (IEEE), pp. 68-78, International Symposium on Performance Analysis of Systems and Software 2019, Madison, United States, 24/03/19 . https://doi.org/10.1109/ISPASS.2019.00015
Kaszyk, J, Wagstaff, H, Spink, T, Franke, B, O'Boyle, M, Bodin, B & Uhrenholt, H 2019, Full-System Simulation of Mobile CPU/GPU Platforms . in Proceedings of the International Symposium on Performance Analysis of Systems and Software 2019 (ISPASS 2019) . Institute of Electrical and Electronics Engineers (IEEE), pp. 68-78, International Symposium on Performance Analysis of Systems and Software 2019, Madison, United States, 24/03/19 . https://doi.org/10.1109/ISPASS.2019.00015
Graphics Processing Units (GPUs) critically rely on a complex system software stack comprising kernel- and userspace drivers and Just-in-time (JIT) compilers. Yet, existing GPU simulators typically abstract away details of the software stack and GPU
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e3744caad1e6ee217c1afc6ee98d468
https://hdl.handle.net/10023/24324
https://hdl.handle.net/10023/24324
Publikováno v:
Kristien, M, Spink, T, Wagstaff, H, Franke, B, Boehm, I & Topham, N 2019, Mitigating JIT Compilation Latency in Virtual Execution Environments . in Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments . Association for Computing Machinery (ACM), pp. 101-107, 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, Providence, United States, 14/04/19 . https://doi.org/10.1145/3313808.3313818
VEE
VEE
Many Virtual Execution Environments (VEEs) rely on Justin-time (JIT) compilation technology for code generation at runtime, e.g. in Dynamic Binary Translation (DBT) systems or language Virtual Machines (VMs). While JIT compilation improves native exe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3184d9a8997a75068fc087362ca731f3
https://hdl.handle.net/10023/24325
https://hdl.handle.net/10023/24325
Publikováno v:
Spink, T, Wagstaff, H & Franke, B 2016, Efficient Asynchronous Interrupt Handling in a Full-System Instruction Set Simulator . in LCTES 2016 Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems . pp. 1-10, 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Santa Barbara, United States, 13/06/16 . https://doi.org/10.1145/2907950.2907953
LCTES
LCTES
Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions usi
Autor:
Luigi Nardi, Sajad Saecdi, Harry Wagstaff, Steve Furber, Bruno Bodin, Andrew J. Davison, Michael F. P. O Boyle, Mikel Luján, Emanuele Vespa, John Mawer, Paul H. J. Kelly, Andy Nisbet
Publikováno v:
Bodin, B, Wagstaff, H, Saecdi, S, Nardi, L, Vespa, E, Mawer, J, Nisbet, A, Lujan, M, Furber, S, Davison, A J, Kelly, P H J & O'Boyle, M F P 2018, SLAMBench2 : Multi-Objective Head-to-Head Benchmarking for Visual SLAM . in 2018 IEEE International Conference on Robotics and Automation, ICRA 2018 ., 8460558, IEEE, pp. 3637-3644, 2018 IEEE International Conference on Robotics and Automation, Brisbane, Australia, 21/05/18 . https://doi.org/10.1109/ICRA.2018.8460558
IEEE International Conference on Robotics and Automation (ICRA)
ICRA
Bodin, B, Wagstaff, H, Saeedi, S, Nardi, L, Vespa, E, Mayer, J H, Nisbet, A, Luján, M, Furber, S, Davison, A J, Kelly, P H J & O'Boyle, M 2018, SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM . in The International Conference in Robotics and Automation 2018 . Institute of Electrical and Electronics Engineers (IEEE), Brisbane, QLD, Australia, pp. 3637-3644, 2018 IEEE International Conference on Robotics and Automation, Brisbane, Australia, 21/05/18 . https://doi.org/10.1109/ICRA.2018.8460558
IEEE International Conference on Robotics and Automation (ICRA)
ICRA
Bodin, B, Wagstaff, H, Saeedi, S, Nardi, L, Vespa, E, Mayer, J H, Nisbet, A, Luján, M, Furber, S, Davison, A J, Kelly, P H J & O'Boyle, M 2018, SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM . in The International Conference in Robotics and Automation 2018 . Institute of Electrical and Electronics Engineers (IEEE), Brisbane, QLD, Australia, pp. 3637-3644, 2018 IEEE International Conference on Robotics and Automation, Brisbane, Australia, 21/05/18 . https://doi.org/10.1109/ICRA.2018.8460558
SLAM is becoming a key component of robotics and augmented reality (AR) systems. While a large number of SLAM algorithms have been presented, there has been little effort to unify the interface of such algorithms, or to perform a holistic comparison
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::46daaaa45e7cdecc147cef35316a1391
https://doi.org/10.1109/ICRA.2018.8460558
https://doi.org/10.1109/ICRA.2018.8460558
Publikováno v:
ISPASS
Bodin, B, Nardi, L, Wagstaff, H, Kelly, P H J & O'Boyle, M 2018, Algorithmic Performance-Accuracy Trade-off in 3D Vision Applications . in 2018 IEEE International Symposium on Performance Analysis of Systems and Software . Institute of Electrical and Electronics Engineers (IEEE), Belfast, UK, pp. 123-124, 2018 IEEE International Symposium on Performance Analysis of Systems and Software, Belfast, United Kingdom, 2/04/18 . https://doi.org/10.1109/ISPASS.2018.00024
Bodin, B, Nardi, L, Wagstaff, H, Kelly, P H J & O'Boyle, M 2018, Algorithmic Performance-Accuracy Trade-off in 3D Vision Applications . in 2018 IEEE International Symposium on Performance Analysis of Systems and Software . Institute of Electrical and Electronics Engineers (IEEE), Belfast, UK, pp. 123-124, 2018 IEEE International Symposium on Performance Analysis of Systems and Software, Belfast, United Kingdom, 2/04/18 . https://doi.org/10.1109/ISPASS.2018.00024
Simultaneous Localisation And Mapping (SLAM) is a key component of robotics and augmented reality (AR) systems. While a large number of SLAM algorithms have been presented, there has been little effort to unify the interface of such algorithms, or to
Publikováno v:
ISPASS
Wagstaff, H, Bodin, B, Spink, T & Franke, B 2017, SimBench: A Portable Benchmarking Methodology for Full-System Simulators . in 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) . Institute of Electrical and Electronics Engineers (IEEE), pp. 217-226, 2017 IEEE International Symposium on Performance Analysis of Systems and Software, Santa Rosa, United States, 24/04/17 . https://doi.org/10.1109/ISPASS.2017.7975293
Wagstaff, H, Bodin, B, Spink, T & Franke, B 2017, SimBench: A Portable Benchmarking Methodology for Full-System Simulators . in 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) . Institute of Electrical and Electronics Engineers (IEEE), pp. 217-226, 2017 IEEE International Symposium on Performance Analysis of Systems and Software, Santa Rosa, United States, 24/04/17 . https://doi.org/10.1109/ISPASS.2017.7975293
We acknowledge funding by the EPSRC grant PAMELA EP/K008730/1. Full-system simulators are increasingly finding their way into the consumer space for the purposes of backwards compatibility and hardware emulation (e.g. for games consoles). For such co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ce5c7f6571f949fe146db5d77072ad4d
https://hdl.handle.net/10023/24317
https://hdl.handle.net/10023/24317
Publikováno v:
Spink, T, Wagstaff, H & Franke, B 2016, ' Hardware Accelerated Cross-Architecture Full-System Virtualization ', ACM Transactions on Architecture and Code Optimization, vol. 13, no. 4, 36 . https://doi.org/10.1145/2996798
Hardware virtualization solutions provide users with benefits ranging from application isolation through server consolidation to improved disaster recovery and faster server provisioning. While hardware assistance for virtualization is supported by a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b8824b60e41ed074057618bb5eff6482
https://hdl.handle.net/20.500.11820/ab3fccd9-365d-4757-8d2c-f62aaeb59791
https://hdl.handle.net/20.500.11820/ab3fccd9-365d-4757-8d2c-f62aaeb59791
Autor:
Luigi Nardi, Christos Kotselidis, Michael O'Boyle, Andy Nisbet, M. Zeeshan Zia, Govind Sreekar Shenoy, Paul H. J. Kelly, John Mawer, Björn Franke, Mikel Luján, Murali Emani, Harry Wagstaff, Bruno Bodin
Publikováno v:
International conference on Parallel Architectures and Compilation Techniques
Bodin, B, Nardi, L, Zia, M Z, Wagstaff, H, Sreekar Shenoy, G, Emani, M K, Mawer, J, Kotselidis, C, Nisbet, A, Luján, M, Franke, B, Kelly, P & O'Boyle, M 2016, Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding . in Parallel Architecture and Compilation Techniques (PACT), 2016 International Conference on . Institute of Electrical and Electronics Engineers (IEEE), pp. 57-69, 25th International Conference on Parallel Architectures and Compilation Techniques, Haifa, Israel, 11/09/16 . https://doi.org/10.1145/2967938.2967963
PACT
Bodin, B, Nardi, L, Zia, M Z, Wagstaff, H, Sreekar Shenoy, G, Emani, M K, Mawer, J, Kotselidis, C, Nisbet, A, Luján, M, Franke, B, Kelly, P & O'Boyle, M 2016, Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding . in Parallel Architecture and Compilation Techniques (PACT), 2016 International Conference on . Institute of Electrical and Electronics Engineers (IEEE), pp. 57-69, 25th International Conference on Parallel Architectures and Compilation Techniques, Haifa, Israel, 11/09/16 . https://doi.org/10.1145/2967938.2967963
PACT
System designers typically use well-studied benchmarks to evaluate and improve new architectures and compilers. We design tomorrow's systems based on yesterday's applications. In this paper we investigate an emerging application, 3D scene understandi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8adc945288aade933758fafaacadb44c
http://hdl.handle.net/10044/1/38354
http://hdl.handle.net/10044/1/38354
Publikováno v:
SAMOS
Spink, T, Wagstaff, H, Franke, B & Topham, N 2015, Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator . in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on . Institute of Electrical and Electronics Engineers (IEEE), pp. 103-112 . https://doi.org/10.1109/SAMOS.2015.7363665
Spink, T, Wagstaff, H, Franke, B & Topham, N 2015, Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator . in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on . Institute of Electrical and Electronics Engineers (IEEE), pp. 103-112 . https://doi.org/10.1109/SAMOS.2015.7363665
Dynamic Binary Translation (DBT) allows software compiled for one Instruction Set Architecture (ISA) to be executed on a processor supporting a different ISA. Some modern DBT systems decouple their main execution loop from the built-inJust-In-Time (J