Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Harmander Singh Deogun"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:1376-1383
Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30c688ec5590d4ac07284011ac37b70f
https://doi.org/10.1109/tvlsi.2005.862718
https://doi.org/10.1109/tvlsi.2005.862718
Autor:
Robert M. Senger, Norman Karl James, Gary D. Carpenter, Alan J. Drake, V. Pokala, Harmander Singh Deogun, Michael Stephen Floyd, Soraya Ghiasi, T. Nguyen
Publikováno v:
ISSCC
A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and VDD droop, or clock stability. It tracks critic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::774736dadaa8d18d0d84eac47af21570
https://doi.org/10.1109/isscc.2007.373462
https://doi.org/10.1109/isscc.2007.373462
Publikováno v:
ISCAS
The exponential increase in leakage power due to technology scaling has made multi-threshold CMOS (MTCMOS) an attractive design style for low-power applications. We explore this design style in a datapath and introduce a fine grained power gating app
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80861f5ace89ab68f905c89791d4a142
https://doi.org/10.1109/iscas.2006.1693468
https://doi.org/10.1109/iscas.2006.1693468
Publikováno v:
ISQED
This paper describes a power gating technique with multiple sleep modes where each mode represents a trade-off between wake-up overhead and leakage savings. We show that high wake-up latency and wake-up power penalty of traditional power gating limit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::284497e8d3d36aee510efb8e63f39e2f
https://doi.org/10.1109/isqed.2006.102
https://doi.org/10.1109/isqed.2006.102
Publikováno v:
ISLPED
In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89be8f61449ad1dd4f7cb914dc989fa5
https://doi.org/10.1145/1165573.1165591
https://doi.org/10.1145/1165573.1165591
Publikováno v:
ISQED
Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d1dd924f63e71e67fb04f13782ae28f
https://doi.org/10.1109/isqed.2005.61
https://doi.org/10.1109/isqed.2005.61
Publikováno v:
ISQED
Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. We present a novel power-gating scheme for repea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09445a99892c4daf0d9a53270ef39efe
https://doi.org/10.1109/isqed.2005.49
https://doi.org/10.1109/isqed.2005.49
Publikováno v:
DAC
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circui
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db3eb91a8db723eaf2b5719d1d8a454b
https://doi.org/10.1145/996566.996776
https://doi.org/10.1145/996566.996776