Zobrazeno 1 - 10
of 72
pro vyhledávání: '"Harish M. Kittur"'
Publikováno v:
Engineering Science and Technology, an International Journal, Vol 18, Iss 2, Pp 135-140 (2015)
In the recent past, Mesh-based clock distribution has received interest due to their tolerance to process variations in deep-sub micron technology. Mesh buffers are placed on the mesh to drive the large load capacitance of clock sinks and mesh wire c
Externí odkaz:
https://doaj.org/article/51727e7108b74b5f9e66956352af3669
Autor:
M. Nithin, Harish M. Kittur
Publikováno v:
WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS. 19:129-142
Phase Locked Loops are key blocks which are widely adopted in all area of electronics, especially transceivers in wireless communication systems. The application of Phase Locked Loop varies from generation of local oscillator signal for upconversion
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75f4556e5808565afb3294d543b7dd15
https://doi.org/10.37394/23201.2020.19.15
https://doi.org/10.37394/23201.2020.19.15
Autor:
Vikas Balikai, Harish M. Kittur
Publikováno v:
Circuit World. 47:71-85
Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32b1127ea6f281bc9100d6c5d1c67bae
https://doi.org/10.1108/cw-11-2019-0184
https://doi.org/10.1108/cw-11-2019-0184
Autor:
Vikas Balikai, Harish M. Kittur
Publikováno v:
Journal of Circuits, Systems and Computers. 30
Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94e4562fef17b30a0b3df54b307e1a3e
https://doi.org/10.1142/s021812662150273x
https://doi.org/10.1142/s021812662150273x
Publikováno v:
Advanced Science Letters. 24:5877-5883
Standard cell libraries are required by all CAD tools for chip planning. Standard cell libraries contain primitive cells required for advanced configuration. Be that as it may, more crucial cells that have been infrequently upgraded can likewise be i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f33736c2648a2b5da6d2624efa998c4
https://doi.org/10.1166/asl.2018.12213
https://doi.org/10.1166/asl.2018.12213
Publikováno v:
2019 2nd International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT).
this paper is presenting the findings of project work that involves finding more efficient and faster circuit logics to bring down the clock skew. Clock skew is the instantaneous difference between the readings of two clocks arrival time. Clocks are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b448f90104367423fe58e076424dad1c
https://doi.org/10.1109/icicict46008.2019.8993375
https://doi.org/10.1109/icicict46008.2019.8993375
Publikováno v:
2019 International Conference on Communication and Signal Processing (ICCSP).
This paper deals with the design of various LC oscillators around 25 GHz which can be used for millimeter wave CMOS radios. Cross coupling is a standard technique used in oscillators and the losses in an LC tank is replenished by the negative resista
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8b32b38f348293f2df9f8e68775df82
https://doi.org/10.1109/iccsp.2019.8697905
https://doi.org/10.1109/iccsp.2019.8697905
Publikováno v:
Scopus-Elsevier
Workflow scheduling is a key problem to be solved in the cloud to increases the quality of services. Few research works have been designed for performing workflow scheduling using different techniques. But, scheduling performance of existing techniqu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::df14203d4a13c037b55881a8970fb2fd
https://doi.org/10.14569/ijacsa.2019.0100441
https://doi.org/10.14569/ijacsa.2019.0100441
Autor:
K. Jagannadha Naidu, Harish M. Kittur
Publikováno v:
Analog Integrated Circuits and Signal Processing. 90:639-644
Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC---DC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f33f644d1901750955bc67686057ef1
https://doi.org/10.1007/s10470-016-0905-z
https://doi.org/10.1007/s10470-016-0905-z
Autor:
K. Jagannadha Naidu, Harish M. Kittur
Publikováno v:
Analog Integrated Circuits and Signal Processing. 89:451-460
System on Chip (SoC) have multiple power domains which operate below the rail voltages and draw very less amount of current. The advancement in VLSI technology has led to direct increase in demand for SoC. As a result of this comprehensive research h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d9852fc6a6400501a70f53436563151
https://doi.org/10.1007/s10470-016-0844-8
https://doi.org/10.1007/s10470-016-0844-8