Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Harish K. Krishnamurthy"'
Autor:
Nachiket Desai, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1090-1099
Autor:
Youssef Elasser, Jaeil Baek, Kaladhar Radhakrishnan, Houle Gan, Jonathan Douglas, Vivek De, Shuai Jiang, Harish K. Krishnamurthy, Xin Li, Charles R. Sullivan, Minjie Chen
Publikováno v:
2023 IEEE Applied Power Electronics Conference and Exposition (APEC).
Autor:
Harish K. Krishnamurthy, Steven K. Hsu, Chris H. Kim, Vivek De, Ram Krishnamurthy, Sriram R. Vangal, Somnath Paul, Amit Agarwal, Saurabh Kumar, James W. Tschanz
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:843-856
The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and application
Autor:
Xiaosen Liu, Vivek De, Sudhir K. Satpathy, Sanu Mathew, Harish K. Krishnamurthy, Krishnan Ravichandran, Himanshu Kaul, Vikram B. Suresh, Mark A. Anders, Raghavan Kumar
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1141-1151
A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While previously reported linear
Autor:
Jin Feng, Kim Suhwan, Huong Do, Sheldon Weng, Vivek De, Harish K. Krishnamurthy, Kaladhar Radhakrishnan, James W. Tschanz, Krishnan Ravichandran, Sally Safwat Amin
Publikováno v:
IEEE Solid-State Circuits Letters. 4:234-237
Autor:
Arijit Raychowdhury, Muya Chang, Shovan Maity, Dong-Hyun Seo, Josef Danial, Sanu Mathew, Harish K. Krishnamurthy, Anupam Golder, Shreyas Sen, Avinash L. Varna, Nirmoy Modak, Debayan Das, Santosh Ghosh, Baibhab Chatterjee
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:136-150
Mathematically secure cryptographic algorithms, when implemented on a physical substrate, leak critical “side-channel” information, leading to power and electromagnetic (EM) analysis attacks. Circuit-level protections involve switched capacitor,
Autor:
Nachiket Desai, Harish K. Krishnamurthy, Suhwan Kim, Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Krishnan Ravichandran, James W. Tschanz, Vivek De
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Claudia P Barrera, Zakir K. Ahmed, Harish K. Krishnamurthy, Xiaosen Liu, Vivek De, Rajasekhara M. Narayana Bhatla, Scott Chiu, James W. Tschanz, Nachiket Desai, Krishnan Ravichandran, Jing Han
Publikováno v:
IEEE Solid-State Circuits Letters. 3:526-529
A dual-rail hybrid analog/digital low-dropout regulator (DRLDO) targeting heterogeneous integration in a multichip package (MCP) platform is presented. Different from the classic single-input–single-output low-dropout regulator (LDO) topology, whic
Autor:
William J. Lambert, Huong Do, Harish K. Krishnamurthy, Sheldon Weng, Nachiket Desai, Vivek De, Christopher Schaef, Kim Suhwan, Khondker Zakir Ahmed, Krishnan Ravichandran, Kaladhar Radhakrishnan, James W. Tschanz, Xiaosen Liu
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:3316-3325
Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The ch
Autor:
Sheldon Weng, Han Wui Then, Nidhi Nidhi, Christopher Schaef, Nicolas Butzen, Jingshu Yu, Marko Radosavljevic, Kaladhar Radhakrishnan, J. Sandford, William J. Lambert, Krishnan Ravichandran, Vivek De, Rode Johann Christian, Nachiket Desai, Sell Bernhard, Harish K. Krishnamurthy, James W. Tschanz
Publikováno v:
VLSI Circuits
A 5V-input, high-frequency, high-density (9A/mm2) buck converter featuring a low-voltage GaN power transistor (with 5-10× better FoM than Si) with on-die gate clamps, integrated with a CMOS companion die in 4mm × 4mm package, achieves 94.2% peak ef