Zobrazeno 1 - 10
of 96
pro vyhledávání: '"Haridimos T. Vergos"'
Publikováno v:
2022 International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52445cf084df18620e0e92a962398d99
https://doi.org/10.1109/iceccme55909.2022.9988065
https://doi.org/10.1109/iceccme55909.2022.9988065
Publikováno v:
Circuits, Systems, and Signal Processing. 34:1041-1056
A Hamming distance comparator (also known as $$k$$k-order comparator) compares its two operands and outputs an agreement if they differ in less than $$k$$k corresponding bits. In this paper, we introduce novel architectures for the design of Hamming
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99a4743714e902a3c8f29de294082b82
https://doi.org/10.1007/s00034-014-9891-5
https://doi.org/10.1007/s00034-014-9891-5
Autor:
George Blanas, Haridimos T. Vergos
Publikováno v:
ICECS
The power signature of an intellectual property (IP) core during its test has been proposed as a watermark that can reveal if it is used without proper authorization within a System on Chip (SoC). In this paper we show that the classic application of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e1f3b45fdfd401e94e3318f424ea67f
https://doi.org/10.1109/icecs.2016.7841187
https://doi.org/10.1109/icecs.2016.7841187
Autor:
Haridimos T. Vergos
Publikováno v:
Integration. 45:388-394
Novel architectures for end-around inverted carry adders are proposed in this manuscript, which use a sparse carry computation unit for deriving only some of the carries in log"2n prefix levels, while all the rest are computed in an extra one. When u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2527d05ce78ce55638cf29e460e6a82
https://doi.org/10.1016/j.vlsi.2011.11.003
https://doi.org/10.1016/j.vlsi.2011.11.003
Autor:
D. Bakalis, Haridimos T. Vergos
Publikováno v:
Microprocessors and Microsystems. 36:409-419
Multi-modulus architectures, that is, architectures that can deal with more than one modulo cases, are very useful for reconfigurable processors and fault-tolerant systems that are based on the residue number system (RNS). Two novel architectures are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6bd9bc40e4d8622cb5d54dc9f5aa671
https://doi.org/10.1016/j.micpro.2012.02.004
https://doi.org/10.1016/j.micpro.2012.02.004
Publikováno v:
Circuits, Systems, and Signal Processing. 30:1445-1461
Novel architectures for designing modulo 2 n +1 subtractors and combined adders/subtractors are proposed in this manuscript. Both the normal and the diminished-one representations of the operands are considered. Unit gate estimates and CMOS VLSI impl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f3881e73255f4f1313f336083d9dcfc
https://doi.org/10.1007/s00034-011-9326-5
https://doi.org/10.1007/s00034-011-9326-5
Publikováno v:
Integration. 44:163-174
Modulo 2^n+/-1 squarers are useful components for designing special purpose digital signal processors that internally use a residue number system and for implementing the modulo exponentiators and multiplicative inverses required in cryptographic alg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74142e1feef8f9622d84e677928c711a
https://doi.org/10.1016/j.vlsi.2011.03.006
https://doi.org/10.1016/j.vlsi.2011.03.006
Autor:
Haridimos T. Vergos, D. Bakalis
Publikováno v:
Journal of Circuits, Systems and Computers. 19:911-930
It is shown that a diminished-1 adder, with minor modifications, can be also used for the modulo 2n + 1 addition of two n-bit operands in the weighted representation, if the sum of its input operands is decreased by one. This modified diminished-1 ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15a92ad8cb85d0861fc75d3564bdc604
https://doi.org/10.1142/s0218126610006529
https://doi.org/10.1142/s0218126610006529
Publikováno v:
Integration. 43:42-48
In this manuscript novel architectures for modulo 2^n+1 multi-operand addition and residue generation are introduced. The proposed arithmetic components consist of a translation stage, an inverted end-around-carry carry-save-adder tree and an enhance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12440500557592958f9051d00f5c379b
https://doi.org/10.1016/j.vlsi.2009.04.002
https://doi.org/10.1016/j.vlsi.2009.04.002
Publikováno v:
Integration. 42:149-157
In this manuscript, we introduce novel carry lookahead (CLA) and parallel-prefix architectures for the design of modulo 2^n+1 adders with operands in the diminished-1 number representation. The proposed architectures are based on the use of Ling carr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4306ad258509bdf0d66b952ca87bf054
https://doi.org/10.1016/j.vlsi.2008.04.004
https://doi.org/10.1016/j.vlsi.2008.04.004