Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Haran Mohit K"'
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Autor:
Patel Reken, P. Plekhanov, S. Rajamani, P. Reese, Conor P. Puls, Muhammet Uncuer, Rahim Kasim, E. Hwang, M. Agostinelli, M. Bost, Swaminathan Sivakumar, S. Nigam, Sanjay Natarajan, P. Charvat, S. Kosaraju, M. Prince, D. Rao, B. Song, M. Yang, S. Williams, P. Yashar, K. S. Lee, Pulkit Jain, I. Jin, Q. Fu, H. Hiramatsu, Kevin J. Fischer, Max M. Heckscher, R. McFadden, V. Chikarmane, Haran Mohit K, A. Rosenbaum, Huichu Liu, D. Bahr, C. Ganpule, C. Pelto, C. Allen
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple