Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Haoyuan Ying"'
Publikováno v:
Journal of Systems Architecture. 59:528-542
3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2f61266da12a4c727591e6ccdab3e88
https://doi.org/10.1016/j.sysarc.2013.03.005
https://doi.org/10.1016/j.sysarc.2013.03.005
Publikováno v:
DDECS
In order to be able to handle an arbitrary amount of static communication segment faults in NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this contribution, we present a flexible and scalable approach for fault-toleranc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26e973e23b73d9a4b11c5467a0579c8f
https://doi.org/10.1109/ddecs.2015.30
https://doi.org/10.1109/ddecs.2015.30
Publikováno v:
HPCS
3-Dimensional Networks-on-Chips (3D NoCs) are proposed as the next generation interconnect infrastructure for multi/many core embedded systems due to the high performance characteristics and scalability. However the heat and thermal issues in 3D NoCs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36ead12ce32b3dc8011bdea833b2872f
https://doi.org/10.1109/hpcsim.2014.6903729
https://doi.org/10.1109/hpcsim.2014.6903729
Publikováno v:
ReCoSoC
In this paper a new latency analysis method for wormhole switched Networks-on-Chip is presented. This method can be used for many wormhole switched NoC with flit interleaving and static routing. The latency estimator is intended to be used for a fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd97f9b1835295a5f05053258c6f90ea
https://doi.org/10.1109/recosoc.2014.6861335
https://doi.org/10.1109/recosoc.2014.6861335
Publikováno v:
ReCoSoC
Network-on-Chip (NoC) is proposed as the next generation interconnect technique for multi/many core embedded systems due to the high performance and scalability. An efficient and correct emulation method is significantly important for NoC system desi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90b124bb7e1ea7176755e4edf87675ac
https://doi.org/10.1109/recosoc.2014.6861336
https://doi.org/10.1109/recosoc.2014.6861336
Publikováno v:
HPCS
As the embedded system design focus moving from computation-centric to communication-centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect components for multi/many core systems due to the scalability and high bandwi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::034e0be018913b299a8090f212f52147
https://doi.org/10.1109/hpcsim.2013.6641417
https://doi.org/10.1109/hpcsim.2013.6641417
Publikováno v:
NORCHIP
The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Vi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ff4e35efeac84afbd2ec7ff52bf47bb
https://doi.org/10.1109/norchp.2012.6403131
https://doi.org/10.1109/norchp.2012.6403131
Publikováno v:
ReCoSoC
3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technologica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49c6b5e4779e3b5091436ebbab096a72
https://doi.org/10.1109/recosoc.2012.6322897
https://doi.org/10.1109/recosoc.2012.6322897
Publikováno v:
HPCS
3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also rais
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa40728903e90c1c9f8286b93d53eba4
https://doi.org/10.1109/hpcsim.2012.6266922
https://doi.org/10.1109/hpcsim.2012.6266922
Publikováno v:
HPCS
3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eed1621aaa9e2a1c5f43fe89bae3ff99
https://doi.org/10.1109/hpcsim.2012.6266923
https://doi.org/10.1109/hpcsim.2012.6266923