Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Hao-Yi Tsai"'
Autor:
Hao-Yi Tsai, 蔡豪益
89
Cu is now being used in ULSI metallization below 0.18 µm as a replacement for Al due to its higher conductivity and higher resistance to electromigration as compared to Al or Al alloy. However, Cu is liable to diffuse into Si and SiO2 and th
Cu is now being used in ULSI metallization below 0.18 µm as a replacement for Al due to its higher conductivity and higher resistance to electromigration as compared to Al or Al alloy. However, Cu is liable to diffuse into Si and SiO2 and th
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/72303185571863420578
Autor:
Hao-Yi Tsai, 蔡豪益
84
Conventional Silicon-based material with an indirect bandgap shows a very poor optical radiative efficiency and only emit light outside the visible range. However, porous silicon pr- epared by electrochemical etching can show a strong visible
Conventional Silicon-based material with an indirect bandgap shows a very poor optical radiative efficiency and only emit light outside the visible range. However, porous silicon pr- epared by electrochemical etching can show a strong visible
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/83059922041260692465
Autor:
Terry Ku, Tsung-Shu Lin, Jeng-Shien Hsieh, Chun Shu-Rong, Douglas Yu, Hao-Yi Tsai, Chung-Shi Liu, Tin-Hao Kuo, Chuei-Tang Wang
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A novel wafer-scale system integration solution, InFO_SoW (System-on-Wafer), has been successfully developed to integrate known-good chips arrays with power and thermal module for high performance computing. InFO_SoW eliminates the use of substrate a
Autor:
Victor C. Y. Chang, C. S. Liu, Jeng-Shien Hsieh, Feng Wei Kuo, Doug C. H. Yu, Hao-Yi Tsai, En-Hsiang Yeh, Chih-Hua Chen, Chewn-Pu Jou, Ron Chen, Ying-Ta Lu, Hsu-Hsien Chen, Chuei-Tang Wang
Publikováno v:
3DIC
An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of −53 dB. With the 3DSI, the RF sy
Autor:
Chao-Hsuing Chen, Rong-Ming Ko, Yi-Cheng Kuo, Kai-Ming Uang, Shui-Jinn Wang, Hao-Yi Tsai, Bor-Wen Liou, Tron-Min Chen
Publikováno v:
Nanotechnology. 17:217-223
The self-synthesis of tungsten oxide (W18O49) nanowires on sputter-deposited W films prepared under different O2/Ar flow rate ratios (OAFRRs) in the sputtering gas is reported. After thermally annealing at 700?850??C in N2 ambient for 15?min, dense a
Publikováno v:
Thin Solid Films. 394:179-187
The barrier properties of sputter-deposited tantalum carbide (TaC x ) and tungsten carbide (WC x ) for Cu metallization were investigated and compared. The incorporation of the C atom is shown to be effective in decorating local defects of the barrie
Autor:
Christine Chiu, Larry Lin, C.H. Yu, H. P. Pu, Bill Kiang, Max K. C. Wu, Patrick Liu, Gary Lu, M. J. Lii, H. Y. Pan, Hao-Yi Tsai, Gene Wu, Kenneth Wu, Tulip Chou
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
In this paper, a novel power cycling system with thermal test vehicle design following the concept defined in JESD22-A122 standard has been established to better approximate field operating conditions. The test unit used in the system is to simulate
Autor:
Wu Kai-Chiang, M. J. Lii, Chen Chia-Hsiang, K. C. Hsu, H.J. Kuo, H. P. Pu, C. H. Lee, M.D. Cheng, C. S. Liu, Chi-Hsi Wu, S.L. Chiu, Hao-Yi Tsai, Douglas Yu, Hsin-Chi Chen, Ching-Wen Hsiao, Chih-Hang Tung
Publikováno v:
2010 International Electron Devices Meeting.
The key technology challenges and solutions in the packaging and assembly of large dies and/or fine pitch on organic substrates for both the 40 and 28 nm technology nodes are reported. Both eutectic PbSn, Pb-free solders, and Cu pillar bumps were use
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
Chip-Package interaction (CPI) has drawn much attention for very low-k (VLK) packaging technology development, especially as the electronic industry is moving from SnPb solder to lead-free solder. In this study, a multi-level finite element model is
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
A new air-gap interconnect scheme with no additional patterning step successfully resolves the issue of unlanded via, and provides good interconnect reliability and improved packaging margin. We demonstrate that the insertion of airgaps in a very low