Výsledky vyhledávání

Dissertation/ Thesis

Run-Time Reconfigurable Superscalar Processor Design

Autor: Hao-I Yang, 楊皓義

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Today, “Information Technology (IT)” develops very fast, and microprocessors play more and more important roles in IT industry. Improving the performance of them is very important. Otherwise, the cost of mask is more and more expansive. H

Externí odkaz: http://ndltd.ncl.edu.tw/handle/86542146318845692301

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A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Autor: Ching-Te Chuang, Yung-Shin Kao, Ya-Ping Wu, Huan-Shun Huang, Shyh-Jye Jou, Wei Hwang, Chien-Yu Lu, Ming-Hsien Tu, Yuh-Jiun Lin, Hao-I Yang, Kuen-Di Lee

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 59:863-867

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::59c2a971d2c5d63e493c84ad8901fcee
https://doi.org/10.1109/tcsii.2012.2231017

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Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-$\kappa$ Metal-Gate Devices

Autor: Ching-Te Chuang, Wei Hwang, Hao-I Yang

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:1192-1204

The threshold voltage (VTH) drifts induced by negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term VTH drifts degrade SRAM cell stability

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8598d113988fdb945a49f0ea7905c5cd
https://doi.org/10.1109/tvlsi.2010.2049038

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Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM

Autor: Hao-I Yang, Wei Hwang, Ching-Te Chuang, Shyh-Chyi Yang

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 58:1239-1251

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-o

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a2a5f023fb8d0c8ec6214265d8ab5291
https://doi.org/10.1109/tcsi.2010.2096112

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Impacts of gate-oxide breakdown on power-gated SRAM

Autor: Wei Hwang, Hao-I Yang, Ching-Te Chuang

Publikováno v: Microelectronics Journal. 42:101-112

This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the read static noise margin (RSNM) and write margin (WM) degrade i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5f18838b4572791084186d6fa2337452
https://doi.org/10.1016/j.mejo.2010.08.020

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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Autor: Chi-Shin Chang, Shyh-Jye Jou, Cheng-Yo Cheng, Nan-Chun Lien, Hao-I Yang, Wei-Chiang Shih, Paul-Sen Kan, Chien-Hen Chen, Wei-Nan Liao, Yi-Wei Lin, Jian-Hao Wang, Ming-Hsien Tu, Ching-Te Chuang, Kuen-Di Lee, Yong-Jyun Hu, Wei Hwang, Wei-Chang Wang, Chia-Cheng Chen, Huan-Shun Huang

Publikováno v: ISCAS

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Wr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cd08d04ceaf2c5ba11e243a1a6b088e9
https://doi.org/10.1109/iscas.2013.6572134

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A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

Autor: Wei Hwang, Hao-I Yang, Wen-Ta Lee, Ya-Ping Wu, Mao-Chih Hsia, Kuen-Di Lee, Nan-Chun Lien, Wei-Chiang Shih, Chih-Chiang Hsu, Yi-Wei Lin, Yung-Wei Lin, Ching-Te Chuang, Chien-Hen Chen

Publikováno v: SoCC

This paper describes an area-efficient variation-tolerant data-aware dynamic supply Write-assist scheme for a cross-point 8T SRAM. A 128Kb test chip implemented in 55nm Standard Performance CMOS technology achieves error free full functionality witho

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cdb580b12784ad5ad8d31965c036de88
https://doi.org/10.1109/socc.2012.6398351

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A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

Autor: Hao-I Yang, Huan-Shun Huang, Chia-Cheng Chen, Chi-Shin Chang, Willis Shih, Yi-Wei Lin, Wei Hwang, Geng-Cing Lin, Ching-Te Chuang

Publikováno v: ISLPED

We present a 55nm 128Kb 6T SRAM with a variation-tolerant dual-tracking Word-Line Under-Drive (WLUD) to improve the RSNM and a Data-Aware Write-Assist (DAWA) scheme. Error free full functionality without redundancy is achieved from 1.5V down to 0.55V

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::071bf35d39ca5f49df1d016aba3cf701
https://doi.org/10.1145/2333660.2333682

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High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Autor: Wei-Chiang Shih, Mao-Chih Hsia, Yin-Nien Chen, Nan-Chun Lien, Chi-Shin Chang, Shyh-Jye Jou, Chih-Chiang Hsu, Geng-Cing Lin, Wen-Ta Lee, Kuen-Di Lee, Hung-Yu Li, Hao-I Yang, Wei Hwang, Ya-Ping Wu, Ching-Te Chuang, Yi-Wei Lin

Publikováno v: ISCAS

This paper presents a 1.0Mb high-performance 0.6V V MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cell

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a9a7eb1899f6ddba2df6509dbb893b98
https://doi.org/10.1109/iscas.2012.6271624

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An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Autor: Shyh-Jye Jou, Yi-Wei Lin, Shao-Cheng Wang, Ching-Te Chuang, Ming-Chien Tsai, Nan-Chun Lien, Geng-Cing Lin, Hao-I Yang, Kuen-Di Lee, Wei-Chiang Shih, Wei Hwang

Publikováno v: VLSI-DAT

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measur

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cc39580d8dc3f885ab3f35f51bd74256
https://doi.org/10.1109/vlsi-dat.2012.6212589

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