Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Hanseok Kim"'
Autor:
Madhan Raj Kanagarathinam, Sukhdeep Singh, Irlanki Sandeep, Hanseok Kim, Mukesh Kumar Maheshwari, Jaehyun Hwang, Abhishek Roy, Navrati Saxena
Publikováno v:
IEEE Access, Vol 8, Pp 164482-164496 (2020)
With the advancement of wireless access networks and mmWave New Radio (NR), new applications emerged, which requires a high data rate. The random packet loss due to mobility and channel conditions in a wireless network is not negligible, which degrad
Externí odkaz:
https://doaj.org/article/ab664f89976047869d0a7bde0d337f2d
Autor:
Van Chien Pham, Hanseok Kim, Jae-Hyuk Choi, Antony J. Nyongesa, Jongsu Kim, Hyeonmin Jeon, Won-Ju Lee
Publikováno v:
Journal of Marine Science and Engineering, Vol 10, Iss 7, p 979 (2022)
Recent developments in power electronics, energy storage systems, and renewable energy; increased market demands for more efficient and cleaner electric power to meet stricter environmental regulations; and development in gigawatt (GW)-class DC (dire
Externí odkaz:
https://doaj.org/article/076db166758d4eacba5bb317d0b8538f
Autor:
Jungbin Yun, Seungjoon Lee, Seungwon Cha, Jihun Kim, Jeongho Lee, Hanseok Kim, Eungkyu Lee, Seonok Kim, Seunghan Hong, Hyungchae Kim, Jinsuk Huh, Sungchul Kim, Kazunori Kakehi, Jae-Ho Kim, June-Mo Koo, Eunsang Cho, Heegeun Jeong, Howoo Park, Kyungho Lee, JungChak Ahn, JoonSeo Yim
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f57d4130d8a5a2514cba59dfe1550fc4
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830254
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830254
Autor:
Hanseok Kim, Woo-Seok Choi
Due to the fundamental limit to reducing power consumption of running deep learning models on von-Neumann architecture, research on neuromorphic computing systems based on low-power spiking neural networks using analog neurons is in the spotlight. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2991b2fa4e5f361fa7ba169a82b820b9
http://arxiv.org/abs/2201.01394
http://arxiv.org/abs/2201.01394
Publikováno v:
KIISE Transactions on Computing Practices. 21:132-137
A real-time system is a system wherein the behavior of the system depends not only on the input but also on the timing of the input. Timed automata is a widely used model for real-time system modeling and analysis. Model-based testing is employed to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19c3ae36f0b294c007728ed3088e951d
https://doi.org/10.5626/ktcp.2015.21.2.132
https://doi.org/10.5626/ktcp.2015.21.2.132
Autor:
Hanseok Kim, Jaeha Kim, Seuk Son, Brian S. Leibowitz, E-Hung Chen, Kyung-hoon Kim, Myeong-Jae Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2693-2704
This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of 0.46 mW/Gbps is made possible by the combination of a direct-feedback f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a380c61b74b4ea77dd44ebaa7ef0df2f
https://doi.org/10.1109/jssc.2013.2274904
https://doi.org/10.1109/jssc.2013.2274904
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
This paper demonstrates a low-power decision feedback equalization (DFE) receiver with 0.46-mW/Gbps efficiency that can compensate up to -15-dB of channel loss while operating at 5-Gb/s. The key is the use of a clocked comparator design that can also
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::869fb0edf3a52528914faa81181ad028
https://doi.org/10.1109/ipec.2012.6522643
https://doi.org/10.1109/ipec.2012.6522643
Publikováno v:
CICC
Dithering in bang-bang controlled CDRs poses conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A novel phase interval detector that looks for a phase interval enclosing th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30ec119f34b2cd252451f0f28ca73b76
https://doi.org/10.1109/cicc.2012.6330683
https://doi.org/10.1109/cicc.2012.6330683
Publikováno v:
ISCAS
A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baed4a76c3d415a8ed372e4d987dbf4a
https://doi.org/10.1109/iscas.2012.6272147
https://doi.org/10.1109/iscas.2012.6272147
Publikováno v:
CICC
This paper presents a methodology of simulating behaviors of complex mixed-signal systems such as phase-locked loops (PLLs) and high-speed I/O interfaces on an event-driven HDL simulator like SystemVerilog. Continuous-time signal events as well as vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06c78a6ac5124663ec5b95409e89ae01
https://doi.org/10.1109/cicc.2011.6055330
https://doi.org/10.1109/cicc.2011.6055330