Zobrazeno 1 - 10
of 49
pro vyhledávání: '"Hans-Jörg Peter"'
Publikováno v:
Mathematical Structures in Computer Science. 23:676-725
We propose a design and verification methodology supporting the early phases of system design for cooperative driver assistance systems, focusing on the realisability of new automotive functions. Specifically, we focus on applications where drivers a
Autor:
Fahim Rahim, Hans-Jörg Peter, Shaker Sarwary, Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
Publikováno v:
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16)
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16), Sep 2016, Tallinn, Estonia. pp.1-6
VLSI-SoC
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'16), Sep 2016, Tallinn, Estonia. pp.1-6
VLSI-SoC
International audience; We propose a novel semi-automatic methodologyto formally verify clock-domain synchronization protocols in industrial-scale hardware designs. Establishing the functional correctness of all clock-domain crossings (CDCs) is cruci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fdb428f39cdffa12c76e3f0375bc6d30
https://hal.archives-ouvertes.fr/hal-01375436
https://hal.archives-ouvertes.fr/hal-01375436
Publikováno v:
IFIP Advances in Information and Communication Technology
24th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSISOC)
24th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.108-129, ⟨10.1007/978-3-319-67104-8_6⟩
IFIP Advances in Information and Communication Technology ISBN: 9783319671031
VLSI-SoC (Selected Papers)
24th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSISOC)
24th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.108-129, ⟨10.1007/978-3-319-67104-8_6⟩
IFIP Advances in Information and Communication Technology ISBN: 9783319671031
VLSI-SoC (Selected Papers)
International audience; We propose a novel semi-automatic methodology to formally verify clock-domain synchronization protocols in industrial-scale hardware designs. To establish the functional correctness of all clock-domain crossings (CDCs) in a sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5dd65965b186af870e52750a6306ec48
https://hal.inria.fr/hal-01675192/file/456609_1_En_6_Chapter.pdf
https://hal.inria.fr/hal-01675192/file/456609_1_En_6_Chapter.pdf
Autor:
Bernd Finkbeiner, Hans-Jörg Peter
Publikováno v:
Electronic Proceedings in Theoretical Computer Science. 84
Publikováno v:
Infotech@Aerospace
The automotive FlexRay standard is increasingly attracting attention in the aeronautics industry. Upgrading existing physical layers, such as CAN-based systems, with FlexRay is attractive, especially given that inexpensive FlexRay hardware is availab
Autor:
Bernd Finkbeiner, Hans-Jörg Peter
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642333644
FORMATS
FORMATS
We revisit the synthesis of timed controllers with partial observability. Bouyer et al. showed that timed control with partial observability is undecidable in general, but can be made decidable by fixing the granularity of the controller, resulting i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bb4ba22fbccb2701cc924bb86b22206
https://doi.org/10.1007/978-3-642-33365-1_15
https://doi.org/10.1007/978-3-642-33365-1_15
Autor:
Bernd Finkbeiner, Hans-Jörg Peter
Publikováno v:
Tools and Algorithms for the Construction and Analysis of Systems ISBN: 9783642287558
TACAS
TACAS
We present an effective controller synthesis method for real-time systems modeled as timed automata with safety requirements. Under the realistic assumption of partial observability, the problem is undecidable in general, and prohibitively expensive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0359d1f21b6b0cd85a31a6dbdebf47a0
https://doi.org/10.1007/978-3-642-28756-5_27
https://doi.org/10.1007/978-3-642-28756-5_27
Publikováno v:
Computer Aided Verification ISBN: 9783642221095
CAV
CAV
We present Synthia, a new tool for the verification and synthesis of open real-time systems modeled as timed automata. The key novelty of Synthia is the underlying abstraction refinement approach [5] that combines the efficient symbolic treatment of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d90d251bce387caf3b2cc03d4d94da4
https://doi.org/10.1007/978-3-642-22110-1_52
https://doi.org/10.1007/978-3-642-22110-1_52
Publikováno v:
RTSS
We present constraint matrix diagrams (CMDs), a novel data structure for the fully symbolic reach ability analysis of timed automata. CMDs combine matrix-based and diagram-based state space representations generalizing the concepts of difference boun
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642152962
FORMATS
FORMATS
We present a general approach to combine symbolic state space representations for the discrete and continuous parts in the synthesis of winning strategies for timed reachability games. The combination is based on abstraction refinement where discrete
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e63cee1aa11d87768856482862a3be7f
https://doi.org/10.1007/978-3-642-15297-9_10
https://doi.org/10.1007/978-3-642-15297-9_10