Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Hanif Fatemi"'
Autor:
Youngmin Shin, Hanif Fatemi, Nathaniel A. Conos, Yun Heo, Seung-jae Jung, Kelvin Le, Jong-Pil Lee, Moon-su Kim
Publikováno v:
DATE
As process technologies are scaled down, interconnect delay becomes major component of entire path delay, and vias represent a significant portion of the interconnect delay. In this paper, a novel variation-aware delay computation method for vias is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::728a9332fbe8b051e465aa9e11964afc
https://doi.org/10.23919/date48585.2020.9116405
https://doi.org/10.23919/date48585.2020.9116405
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:749-759
Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6c1aec1579c0579c1623a9dee5c12e04
https://doi.org/10.1109/tcad.2010.2043570
https://doi.org/10.1109/tcad.2010.2043570
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1495-1508
As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by sigmaTA) is becoming unavoidable. In this paper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05d10a2cbdb25e3f940be71e1f8f55fb
https://doi.org/10.1109/tcad.2007.893552
https://doi.org/10.1109/tcad.2007.893552
Publikováno v:
DATE
This paper presents a current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell. Characterization procedures for various compo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49c86f2a74b1e80e115984d85632da89
https://doi.org/10.1145/1403375.1403514
https://doi.org/10.1145/1403375.1403514
Publikováno v:
ISLPED
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors to reduce the leakage power consumption in the idle mode is used. We si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10b9529fd9a6eaaccb3500b188fc0be8
https://doi.org/10.1145/1283780.1283802
https://doi.org/10.1145/1283780.1283802
Publikováno v:
DATE
In this paper, a method is proposed for finding a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified image distortion level for a liquid crystal display. This is achieved by finding a pixel transformation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0fb20c0207ce9cb89190973058b934cf
Publikováno v:
ASP-DAC
An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage values. Therefore the actual shape of the voltage signal waveforms at the i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74fb916d63c944e78199a3e856473b09
https://doi.org/10.1109/aspdac.2007.358083
https://doi.org/10.1109/aspdac.2007.358083
Publikováno v:
ICCD
As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to gate and wire variability. Therefore, statistical timing analysis is inevitable. Most timing tools divide the analysis into two p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef8f3d0ad7a17e7a9940108a9b9d02f6
https://doi.org/10.1109/iccd.2005.115
https://doi.org/10.1109/iccd.2005.115
Publikováno v:
ACM Great Lakes Symposium on VLSI
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a significant impact on both device (front-end of the line) and interconne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fadc175cb34495ef6a98073353a22d27
https://doi.org/10.1145/1127908.1127965
https://doi.org/10.1145/1127908.1127965
Publikováno v:
DATE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performing timing analysis of RLC networks with step inputs, under both Gaussian
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f88d714ab854cbd14d5174ec9021134e
https://doi.org/10.1109/date.2006.243891
https://doi.org/10.1109/date.2006.243891