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Akademický článek

The Development of Medical Record Items: a User-centered, Bottom-up Approach

Autor: YoungAh Kim, Hangi Park, Hong-Gee Kim, Yong Oock Kim

Publikováno v: Healthcare Informatics Research, Vol 18, Iss 1, Pp 10-17 (2012)

ObjectivesClinical documents (CDs) have evolved from traditional paper documents containing narrative text information into the electronic record sheets composed of itemized records, where each record is expressed as an item with a specific value. We

Externí odkaz: https://doaj.org/article/e509e75195054af4846fc3e6a5c01c88

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An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators

Autor: Yoonseo Cho, Heein Yoon, Jaehyouk Choi, Juyeop Kim, Hangi Park, Taeho Seong, Yongsun Lee, Younghyun Lim

Publikováno v: IEEE Journal of Solid-State Circuits. 54:3466-3477

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::403d433895911bbf24f7627b6110b184
https://doi.org/10.1109/jssc.2019.2936765

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32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM

Autor: Hangi Park, Taeho Seong, Chanwoong Hwang, Jaehyouk Choi, Yongsun Lee

Publikováno v: ISSCC

To maximize data-rates by combining more carrier components, 5G RF transceivers require many carrier frequencies, resulting in the situation of many LC PLLs occupying a large silicon area. Ring-oscillator-based digital PLLs (RO-DPLLs) with a fraction

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c448b9704c07b34c0726f81ee137c049
https://doi.org/10.1109/isscc42613.2021.9365798

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32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique

Autor: Juyeop Kim, Taeho Seong, Yongwoo Jo, Seojin Choi, Hangi Park, Younghyun Lim, Seyeon Yoo, Yongsun Lee, Jaehyouk Choi

Publikováno v: ISSCC

Subsampling PLLs (SSPLLs) are attractive architectures to generate ultra-low-jitter RF signals due to their intrinsically high phase-error-detection gain, K SH . However, this high-gain operation of a sample-and-hold circuit (SH) also has a downside

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d50578a72fb91ab21b736550d2da075c
https://doi.org/10.1109/isscc42613.2021.9365815

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17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word

Autor: Yongsun Lee, Jaehyouk Choi, Taeho Seong, Hangi Park, Chanwoong Hwang, Jeonghyun Lee, Kyuho Jason Lee

Publikováno v: ISSCC

Despite their superiority in silicon integration, ring-oscillator-based digital PLLs (RO-DPLLs) are seldom used for mobile transceivers because they have difficulty in meeting key requirements, such as low phase noise (PN) and high-frequency resoluti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c72a2ea91b1ebea17fc32f79e24f244c
https://doi.org/10.1109/isscc19947.2020.9062948

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17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction

Autor: Yongsun Lee, Hangi Park, Taeho Seong, Chanwoong Hwanq, Jaehyouk Choi, Jeonghyun Lee

Publikováno v: ISSCC

Methods to detect and correct timing errors of oscillators are very important to achieve the low-jitter performance of a ring-DCO (RDCO) digital PLL (DPLL). A TDC is widely used to quantize these timing errors. The higher the resolution of a TDC, the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1f87d38203c7fba5f4135acf0b38909b
https://doi.org/10.1109/isscc19947.2020.9062966

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17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator

Autor: Hangi Park, Yongwoo Jo, Juyeop Kim, Younghyun Lim, Jooeun Bang, Seyeon Yoo, Heein Yoon, Jaehyouk Choi

Publikováno v: ISSCC

Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However, the critical problem of SSPLLs is that they do not use a frequency divider, so the lock-in range is strictly limited. The lock-in range is defined as the maximu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::36dd1abb68b5ed9ac9d02038b24faa2a
https://doi.org/10.1109/isscc19947.2020.9062921

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