Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Han-Liang Chou"'
Autor:
Andy-HB Wang, Tung-Hsing Wu, Abrams Chen, Wayne Hsieh, Ch Wang, Chen-Yen Ho, Sokonisa Wei, Wc Gu, Chang-Hung Tsai, Hue-Min Lin, Chih-Ming Wang, Larry Chu, Chang Jing-Ying, Yung-Chang Chang, Kevin Jou, Han-Liang Chou, Chi-cheng Ju, Ying-Jui Chen, Shou-Chun Liao, Tsu-Ming Liu
Publikováno v:
ISSCC
A 2MPixels@30fps 24b high-dynamic-range image processing chip is fabricated in a 16nm CMOS process with a core area of 5.69mm2. This LSI integrates multiple color-filter-array (RGGB, RGB-Ir, RCCC, RCCB, and Mono) image processing into a single chip.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2aa6f5ef7b952b470161cda3cfba20a
https://doi.org/10.1109/isscc19947.2020.9063063
https://doi.org/10.1109/isscc19947.2020.9063063
A 0.76 mm2 0.22 nJ/Pixel DL-Assisted 4K Video Encoder LSI for Quality-of-Experience Over Smartphones
Autor:
Jia-Ying Lin, Tung-Hsing Wu, Han-Liang Chou, Chi-cheng Ju, Chen Li-Heng, Tsu-Ming Liu, Chang-Hung Tsai, Yung-Chang Chang
Publikováno v:
IEEE Solid-State Circuits Letters. 1:221-224
This letter proposes the world’s first deep learning (DL)-assisted video encoder LSI fabricated in a 10-nm process with a core area of 0.76 mm2 to integrate quad-core DL accelerators and $4\text{K}\times 2\text{K}$ H.264/H.265 video encoders. A vis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f90904706aa0093790f70f2fd8f9d85c
https://doi.org/10.1109/lssc.2019.2905958
https://doi.org/10.1109/lssc.2019.2905958
Autor:
Chun-Chia Chen, Tsu-Ming Liu, Min-Hao Chiu, Tung-Hsing Wu, Chi-cheng Ju, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Peng-Hao Wang, Yen-Chao Huang, Chih-Ming Wang, Ping Chao, Hsiu-Yi Lin, Ming-Long Wu, Meng-Jye Hu, Yu-Kun Lin, Ting-An Lin, Chia-Yun Cheng, Che-Hong Chen, Sheng-Jen Wang, Shun-Hsiang Chuang, Han-Liang Chou, Chen Lien-Fei, Hue-Min Lin, Yung-Chang Chang, Chih-Da Chien, Kun-bin Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:56-67
A 4 K $\,\times\,$ 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.49 $\,\times\,$ 1.45 mm $^{2}$ die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content fe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4237a07f3493efd5831e6195d5e3fa3a
https://doi.org/10.1109/jssc.2015.2465857
https://doi.org/10.1109/jssc.2015.2465857
Autor:
Chi-cheng Ju, Chen Li-Heng, Chang-Hung Tsai, Han-Liang Chou, Tsu-Ming Liu, Tung-Hsing Wu, Jia-Ying Lin
Publikováno v:
VLSI Circuits
This paper proposes the world's first deep learning (DL)-assisted video encoder LSI fabricated in a 10nm process with a core area of 0.76mm2 to integrate quad-core DL accelerators and 4K×2K H.264/H.265 video standards. A visual-contact-field network
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e13270415abce405ed147b8884eada5a
https://doi.org/10.1109/vlsic.2018.8502304
https://doi.org/10.1109/vlsic.2018.8502304
Autor:
Min-Hao Chiu, Yu-Kun Lin, Peng-Hao Wang, Tsu-Ming Liu, Yen-Chao Huang, Ping Chao, Kun-bin Lee, Han-Liang Chou, Hue-Min Lin, Chen Lien-Fei, Ryan Chen, Yung-Chang Chang, Ming-Long Wu, Kevin Jou, Wei-Cing Li, Yen-Chieh Lai, Yi-Hsin Huang, Che-Hong Chen, Tung-Hsing Wu, H Y Hsu, Sheng-Jen Wang, Chih-Da Chien, Ting-An Lin, Shun-Hsiang Chuang, Chun-Chia Chen, Chi-cheng Ju, Hsiu-Yi Lin, Chin-Ming Wang, Meng-Jye Hu, Chia-Yun Cheng, Fu-Chun Yeh
Publikováno v:
ISSCC
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220b21ba0bbb83d403b694f7b2e5d1cb
https://doi.org/10.1109/isscc.2015.7063063
https://doi.org/10.1109/isscc.2015.7063063
Autor:
Yung-Chang Chang, Min-Hao Chiu, Kun-bin Lee, Chi-cheng Ju, Yi-Hsin Huang, Chih-Ming Wang, Yi-Hau Chen, Han-Liang Chou, Sheng-Jen Wang, Hsueh-Te Chao, Tung-Hsing Wu, Yu-Kun Lin, Chun-Chia Chen, Tin-An Lin, Hue-Min Lin, Tsu-Ming Liu, Tsung-Chuan Ma, Cheng-Hung Liu, Chia-Yun Cheng, Wei-Cing Li, Chung-Hung Tsai
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Sev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13821c7e7af4b566598d2b9c2fd9fa9b
https://doi.org/10.1109/ipec.2012.6522611
https://doi.org/10.1109/ipec.2012.6522611
Autor:
Han-Liang Chou, 周漢良
89
This thesis provides the design and implementation issues of the shape encoding core: CAE (Context-based Arithmetic Encoding) for the MPEG-4 video encoder (Core Profile). This CAE unit is encapsulated by the interface protocol: VSI Alliance-
This thesis provides the design and implementation issues of the shape encoding core: CAE (Context-based Arithmetic Encoding) for the MPEG-4 video encoder (Core Profile). This CAE unit is encapsulated by the interface protocol: VSI Alliance-
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/86510846502275482810
Autor:
Lu, Qianyun, Murmann, Boris
Publikováno v:
ACM Transactions on Embedded Computing Systems; May2024, Vol. 23 Issue 3, p1-20, 20p
Publikováno v:
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers; 2015, p516-521, 6p
Autor:
Ju, Chi-Cheng, Liu, Tsu-Ming, Lee, Kun-Bin, Chang, Yung-Chang, Chou, Han-Liang, Wang, Chih-Ming, Wu, Tung-Hsing, Lin, Hue-Min, Huang, Yi-Hsin, Cheng, Chia-Yun, Lin, Ting-An, Chen, Chun-Chia, Lin, Yu-Kun, Chiu, Min-Hao, Li, Wei-Cing, Wang, Sheng-Jen, Lai, Yen-Chieh, Chao, Ping, Chien, Chih-Da, Hu, Meng-Jye
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2016, Vol. 51 Issue 1, p56-67, 12p