Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Han-Jan Tao"'
Autor:
Shih-Chang Chen, Fu-Liang Yang, Jiunn-Ren Hwang, Yi-Ming Sheu, Cheng-Kuo Wen, Hung-Ming Chen, Chang-Yun Chang, Han-Jan Tao, Chien-Chao Huang, Ming-Yi Yang
Publikováno v:
Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials.
Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm/sup 2/ 6T-SRAM cell by immersion lithography
Autor:
null Hou-Yu Chen, null Chang-Yun Chang, null Chien-Chao Huang, null Tang-Xuan Chung, null Sheng-Da Liu, null Jiunn-Ren Hwang, null Yi-Hsuan Liu, null Yu-Jun Chou, null Hong-Jang Wu, null King-Chang Shu, null Chung-Kan Huang, null Jan-Wen You, null Jaw-Jung Shin, null Chun-Kuang Chen, null Chia-Hui Lin, null Ju-Wang Hsu, null Bao-Chin Perng, null Pang-Yen Tsai, null Chi-Chun Chen, null Jyu-Horng Shieh, null Han-Jan Tao, null Shih-Chang Chen, null Tsai-Sheng Gau, null Fu-Liang Yang
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate de
Autor:
Chien-Chao Huang, Jyu-Horng Shieh, Jam-Wem Lee, Hou-Yu Chen, Hung-Wei Chen, Chang-Yun Chang, Chi-Chun Chen, Chenming Hu, Tang-Xuan Chung, Shih-Chang Chen, Yee-Chia Yeo, Di-Hong Lee, Cheng-Chuan Huang, Fu-Liang Yang, C.H. Chen, Yiming Li, Pu Chen, Mong-Song Liang, Han-Jan Tao, Peng-Fu Hsu, C.C. Wu, Ying-Tsung Chen, Yi-Hsuan Liu, Bor-Wen Chan, Ying-Ho Chen, Sheng-Da Liu
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 p
Publikováno v:
2003 8th International Symposium Plasma- and Process-Induced Damage..
In this communication we report our work on the ashing of post high dosage implant photoresist removal. Attention is focused on plasma damage to the silicon substrate, in addition to hard skin removal capabilities. An inductively coupled plasma (ICP)
Publikováno v:
2003 8th International Symposium Plasma- & Process-Induced Damage; 2003, p73-76, 4p
Akademický článek
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Autor:
Jaw-Jung Shin, Fu-Jye Liang, Ming Lu, Li-Wei Kung, Fu-Liang Yang, Chien-Chao Huang, Hsun-Chih Tsao, Cheng-Kuo Wen, Jhon-Jhy Liaw, Ke-Wei Su, Yu-Jun Chou, Yi-Chun Huang, Yung-Shun Chen, Di-Hong Lee, Tze-Liang Lee, Shui-Ming Cheng, Samuel Fung, Chenming Hu, Bin-Chang Chang, Tang-Xuan Chung, Chuan-Ping Hou, Chang-Yun Chang, Tsai-Sheng Gau, Kuang-Hsin Chen, J.Y.-C. Sun, Cheng Chuan Huang, Hou-Yu Chen, Jan-Wen You, Liang Min-Chang, Jhi-cheng Lu, Chi-Chun Chen, Burn-Jeng Lin, Kuei-Shun Chen, Yee-Chia Yeo, Han-Jan Tao, J.H. Chen, Shih-Chang Chen, Hung-Wei Chen, Carlos H. Diaz, Yi-Ming Sheu, Chun-Kuang Chen, Bor-Wen Chan, Ying-Ho Chen, W. Chang, King-Chang Shu, C.H. Chen, Chii-Ming Wu, Cheng-hung Chang
Publikováno v:
Scopus-Elsevier
A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d2cd43133598ebbb8ca11a12eccb16a1
http://www.scopus.com/inward/record.url?eid=2-s2.0-17644444298&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-17644444298&partnerID=MN8TOARS
Autor:
Hou-Yu Chen, Chang-Yun Chang, Chien-Chao Huang, Tang-Xuan Chung, Sheng-Da Liu, Jiunn-Ren HwangYi-Hsuan Liu, Yu-Jun Chou, Hong-Jang Wu, King-Chang Shu, Chung-Kan Huang, Jan-Wen You, Jaw-Jung Shin, Chun-Kuang Chen, Chia-Hui Lin, Ju-Wang Hsu, Bao-Chin Perng, Pang-Yen Tsai, Chi-Chun Chen, Jyu-Horng Shieh, Han-Jan Tao
Publikováno v:
2005 Digest of Technical Papers. 2005 Symposium on VLSI Technology; 2005, p16-17, 2p
Autor:
Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao
Publikováno v:
2004 Digest of Technical Papers. 2004 Symposium on VLSI Technology; 2004, p196-197, 2p