Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Hamidreza Esmaeili Taheri"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:315-324
Publikováno v:
Analog Integrated Circuits and Signal Processing. 96:373-384
A new adaptive bandwidth, adaptive jitter frequency synthesizer is proposed. This synthesizer is designed in such a way that the ratio of bandwidth to the reference frequency is kept approximately fixed in order to maintain the optimum jitter perform
Publikováno v:
AEU - International Journal of Electronics and Communications. 131:153599
In this paper, the design and implementation of a low-power, high-resolution, fully differential readout architecture for capacitive sensing applications is presented. The proposed sensing mechanism is based on the gain variations of two capacitively
Publikováno v:
2017 Iranian Conference on Electrical Engineering (ICEE).
A new adaptive bandwidth adaptive jitter phase locked loop (PLL) is proposed and simulated. This circuit maintains an almost fixed bandwidth to reference frequency ratio and hence, jitter performance is kept unchanged. The main idea is to change the