Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Hamid Savoj"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:919-930
This paper introduces ${m}$ -inductiveness over a set of nodes ${S}$ in sequential circuits. The ${m}$ -inductive property can be used for equivalence-checking or improved sequential optimization. It allows the behavior of many next state functions (
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:305-317
Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence
Publikováno v:
Journal of Chemical Information and Computer Sciences. 34:1297-1308
Publikováno v:
ISCAS (3)
This paper presents a physical synthesis methodology for ASIC datapath modules. It exploits the regularity information of datapath circuits and integrates the synthesis and placement processes together. This work is distinctive in the following aspec
Publikováno v:
ICCAD
Two methods for two-level logic minimization tuned to a multilevel network environment are discussed. Each produces results superior to ESPRESSO. The tautology-based method is very simple and can be coded in less than 700 lines of C language using th
Autor:
Robert K. Brayton, K.J. Singh, Alberto Sangiovanni-Vincentelli, Hamid Savoj, E.M. Sentovich, Cho W. Moon
Publikováno v:
ICCD
A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology
Publikováno v:
ICCAD
The authors propose a novel technology-independent algorithm to minimize circuit delay. The algorithm works in two steps. The first step performs a partial collapse of the circuit based on a delay-driven clustering. The second step factorizes and sim
Publikováno v:
ICCAD
An algorithm for computing local don't cares (in terms of immediate fanin variables) at each intermediate node of a Boolean network is presented. These don't cares can be directly used for the simplification of each node by a two-level minimizer. The
Autor:
Robert K. Brayton, Hamid Savoj
Publikováno v:
ICCAD
The observability relation O(x,z) or the Boolean relation provides a description of all the flexibility one has in implementing a Boolean network N. The authors represent and use this flexibility in a logic synthesis system by adding a single output
Publikováno v:
ICCAD
Scopus-Elsevier
Scopus-Elsevier
The authors propose a novel method based on transition relations that only requires the ability to compute the BDD (binary decision diagram) for f/sub i/ and outperforms O. Coudert's (1990) algorithm for most examples. The method offers a simple nota