Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Hakjune Oh"'
Autor:
Peter Gillingham, David Chinn, Eric Choi, Jin-Ki Kim, Don Macdonald, Hakjune Oh, Hong-Beom Pyeon, Roland Schuetz
Publikováno v:
IEEE Access, Vol 1, Pp 811-816 (2013)
A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip
Externí odkaz:
https://doaj.org/article/1e28e67caa6b49eb9ddc2b3dfcf90a22
Autor:
Roland Schuetz, David Chinn, Jin-Ki Kim, Peter B. Gillingham, Hakjune Oh, Don Macdonald, Hong-Beom Pyeon, Eric T. Choi
Publikováno v:
IEEE Access, Vol 1, Pp 811-816 (2013)
A 256 Gb NAND flash memory multi-chip package (MCP) includes eight stacked 32 Gb 2 bit/cell multi-level cell (MLC) die and an 11.6 mm2 HyperLink NAND bridge chip providing four internal NAND channels for concurrent memory operations. The bridge chip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c77a7c669889ff95582b13facb83e469
https://ieeexplore.ieee.org/document/6681893/
https://ieeexplore.ieee.org/document/6681893/
Autor:
Jin-Ki Kim, Roland Schuetz, Don Macdonald, Eric Choi, David Chinn, Hong-Beom Pyeon, Peter B. Gillingham, Hakjune Oh
Publikováno v:
2011 3rd IEEE International Memory Workshop (IMW).
A 256Gb NAND flash device includes eight stacked 32Gb MLC die and a 16.2mm 2 HLNAND interface chip providing a 300MB/s synchronous DDR point-to-point ring topology system interface. Four internal busses supporting both 40MHz asynchronous NAND or 133M
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28aa3f2f51bca674ff4d0ad7a33352f1
https://doi.org/10.1109/imw.2011.5873241
https://doi.org/10.1109/imw.2011.5873241
Autor:
Roland Schuetz, Hong-Beom Pyeon, Peter B. Gillingham, Jin-Ki Kim, Steven Przybylski, Hakjune Oh
Publikováno v:
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.
The dramatic price reduction of NAND Flash devices in recent years has created an opportunity for Flash to penetrate mass storage applications. This will happen provided the memory vendors can deliver NAND Flash devices with adequate performance and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be3e3ad75809579cd2a5fd849355e89d
https://doi.org/10.1109/nvsmw.2007.4290560
https://doi.org/10.1109/nvsmw.2007.4290560
Publikováno v:
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.
Voltage stress during programming is a major factor limiting reliability in NAND Flash memory. To control programming stress several desirable features such as random page program, partial page program, and low Vcc operation are eliminated or restric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ba3bbe0a33f3715980d62cd8a80c54e
https://doi.org/10.1109/nvsmw.2007.4290563
https://doi.org/10.1109/nvsmw.2007.4290563
A 256Gb NAND Flash Memory Stack with 300MB/s HLNAND Interface Chip for Point-to-Point Ring Topology.
Autor:
Gillingham, P., Jin-Ki Kim, Schuetz, R., Hong-Beom Pyeon, HakJune Oh, Macdonald, D., Choi, E., Chinn, D.
Publikováno v:
2011 3rd IEEE International Memory Workshop (IMW); 2011, p1-3, 3p
Publikováno v:
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop; 2007, p19-20, 2p
Publikováno v:
2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop; 2007, p3-4, 2p