Zobrazeno 1 - 10
of 18
pro vyhledávání: '"H.V. Meer"'
Autor:
C.W. Huang, L. Holcman, D. Fung, H.V. Meer, C.F. Hsu, C.H. Chen, J. Fernandez, Benjamin Colombeau, Y.T. Tasi, B.N. Guo, H.P. Chen, Kyu-Ha Shim, J. Kuo, H.C. Feng, M. Hou, S.A. Huang, K. Nafisr, S.Y. Liu, J.C. Lin, T.Y. Wen, G.C. Hung, C.l. Li, S. Lee, N.H. Yang, B. Yang, J.Y. Wu, C.C. Huang
Publikováno v:
2019 Symposium on VLSI Technology.
In advanced FinFET devices, STI gap fill and $\vert \text{LD}_{0}$ stress are responsible for fin defects, fin bending as well as device performance degradations due to the local layout effect (LLE). In this paper, for the first time, we look at diff
Autor:
C. I. Li, M.S. Hsieh, Y. Zhang, J.Y. Wu, H.V. Meer, S. Lee, H.-J. Gossmann, B.N. Guo, Kyu-Ha Shim, T.Y. Wen, H.T. Chiang, Benjamin Colombeau, S.H. Lin, D. Liao, N.H. Yang, Jeff Kuo, M. Hou, S.H. Tsai, P.K. Hsieh
Publikováno v:
2018 22nd International Conference on Ion Implantation Technology (IIT).
FinFET doping via implantation at room temperature could result in Fin damage within the Fin body and degrade Fin device performance. Heated implantation techniques are developed to address the detrimental effects on devices caused by the damage. The
Akademický článek
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Autor:
Eduard A. Cartier, X. Chen, Pierre Malinge, L. Kang, T. Watanabe, Michael P. Belyansky, L. Economikos, O. Menut, Vijay Narayanan, C. Reddy, R. Divakaruni, Y.H. Park, Ravi Prakash Srivastava, M. Pallachalil, R. Koshy, Dominic J. Schepis, P. Montanini, Keith Kwong Hon Wong, M. Eller, Park Sejun, A. Ogino, H. Mallela, U. Kwon, T. Shimizu, W. Cote, Jay W. Strane, Srikanth Samavedam, M. Chae, Anurag Mittal, R. Sampson, J. Meiring, R. Joy, Huiling Shang, S. Soss, X. Yang, Keith H. Tabakman, M. Oh, W. Lai, C. Tran, S. Jain, E. Josse, D. Codi, H.V. Meer, B.Y. Kim, Jung-Geun Kim, Jin Bum Kim, C. Goldberg, Henry K. Utomo, J. Ciavatti, Barry Linder, R. Vega, W. Neumueller, J. Muncy, Kyung-hwan Cho, Scott J. Bukofsky, Alvin G. Thomas, Dinesh Koli, Katherina Babich, Bomi Kim, S. Lian, E. Alptekin, Y. Liu, S. H. Rhee, X. Wu, R. Arndt, W.L. Tan, Frederic Lalanne, Nam-Sung Kim, Ravikumar Ramachandran, K.Y. Lee, M.H. Nam, Randy W. Mann, Il-Ryong Kim, Yujun Li, V. Sardesai, Siddarth A. Krishnan, C. Tian, D. Levedakis, Seung-Kwon Kim, Jedon Kim, M. Celik, F. Matsuoka, M. Weybright, J. Sudijono, M. Aminpur, B. Hamieh, Greg Northrop, J.W. Lee
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared w
Autor:
J. Yuan, C. Gruensfelder, K. Y. Lim, T. Wallner, M. K Jung, M. J. Sherony, Y. M. Lee, J. Chen, C. W. Lai, Y.T. Chow, K. Stein, L. Y. Song, H. Onoda, C. W. An, H. Wang, B. K. Moon, J. Kim, H. Inokuma, H. Yamasaki, J. Shah, H.V. Meer, S. B. Samavedam, Q. T. Zhang, C. Zhu, Y. Park, Y. E. Lim, R. Nieuwenhuizen, J. P. Han, M. Hamaguchi, W.L. Lai, M. P. Belyansky, O. Gluschenkov, S. Johnson, R. Divakaruni, E. F. Kaste, J. Sudijono, J. H. Ku, F. Matsuoka, W. Neumueller, R. Sampson, M. Sekine, A. Steegen
Publikováno v:
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.
In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique
Autor:
D. Schepis, C.Y. Sung, H. Yin, B. Kim, B. Yang, M. Khare, L. Black, C. D. Sheraw, Donggun Park, H.V. Meer, X. Chen, J. Johnson, Andrew Waite, K. Nummy, H. Gossmann, P. Agnello, Philip A. Fisher, Scott Luning, S. Narasimha, D. Chidambarrao, Judson R. Holt, S. D. Kim, D. Wehella-gamage, Y. Liu
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong cha
Autor:
Byeong Y. Kim, Richard A. Wachnik, Hasan M. Nayfeh, Henry K. Utomo, Mukesh Khare, Jian Yu, Jinping Liu, Anthony G. Domenicucci, Haizhou Yin, Shreesh Narasimha, B. Yang, Dureseti Chidambarrao, R. Pal, Keith H. Tabakman, Seong-Dong Kim, Dominic J. Schepis, Z. Luo, Effendi Leobandung, Brian J. Greene, S.H. Ku, Paul D. Agnello, X. Wang, Q. Liang, Andrew Waite, L. Black, Scott Luning, Chun-Yung Sung, Gregory G. Freeman, Y. Wang, K. Nummy, H.V. Meer, Philip A. Fisher, Edward P. Maciejewski, X. Chen, D.-G. Park, Judson R. Holt
Publikováno v:
2007 IEEE International Electron Devices Meeting.
This paper presents for the first time (110) PMOS characteristics without Rext degradation, allowing investigation of fundamental mobility and demonstration of drive current Ion in excess of 1mA/mum at Ioff =100 nA/μm.
Autor:
S. Subbanna, Huilong Zhu, T. Shinohara, R.-V. Bentum, H. Kuroda, C. Penny, Jay W. Strane, D. McHerron, D. Harmon, D. Zamdmer, Q. Ye, Yoshiaki Toyoshima, Paul D. Agnello, S. Wu, G. Freeman, L. Tsou, Atsushi Azuma, Scott J. Bukofsky, Carl J. Radens, M. Angyal, M. Fukasawa, Effendi Leobandung, Byeong Y. Kim, M. Gerhardt, Y. Tan, L. Su, Tenko Yamashita, Anda Mocuta, I.C. Inouc, Takeshi Nogami, Scott D. Allen, R. Logan, K. Miyamoto, Shih-Fen Huang, Ravikumar Ramachandran, J. Pellerin, A. Ray, Siddhartha Panda, Christine Norris, H.V. Meer, H. Nayakama, Mizuki Ono, Keith Jenkins, J. Heaps-Nelson, Wenjuan Zhu, D. Ryan, Michael A. Gribelyuk, B. Dirahoui, M. Inohara, E. Nowak, I. Melville, S. Lane, T. Ivers, K. Ida, Scott Halle, Ishtiaq Ahsan, M.-F. Ng, Huicai Zhong, H. Harifuchi, S.-K. Ku, N. Kepler, F. Wirbeleit, Emmanuel F. Crabbe, H. Yan, T. Kawamura, Mahender Kumar, A. Nomura, L. K. Wang, F. Sugaya, H. Hichri, Gary B. Bronner, P. O'Neil, K. Miyashita, Michael P. Belyansky, J. Cheng, S.-H. Rhee, Lars W. Liebmann, D. Yoneyama, Dan Mocuta, K. McStay, G. Sudo, Dureseti Chidambarrao
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL en
Conference
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Conference
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