Zobrazeno 1 - 10
of 108
pro vyhledávání: '"H.R. Rategh"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1015-1027
Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). An important attribute is substantially lower power consumption relative to their digital counterparts. The model des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d0a0f3e143755ca41fc0d5771ffeae5
https://doi.org/10.1109/jssc.2003.811975
https://doi.org/10.1109/jssc.2003.811975
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 50:268-280
This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-/spl mu/m CMOS logic technology,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4b73e965ad757bfe8a7205549d904e9
https://doi.org/10.1109/22.981280
https://doi.org/10.1109/22.981280
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:780-787
A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (IL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f44ae3478630e2bec30e5e527573b2fe
https://doi.org/10.1109/4.841507
https://doi.org/10.1109/4.841507
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:765-772
This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2e4af0aa654fd8ec25e155e2589f1c8
https://doi.org/10.1109/4.841505
https://doi.org/10.1109/4.841505
Autor:
H.R. Rategh, Thomas H. Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:813-821
Injection-locked oscillators (ILOs) are investigated in a new theoretical approach. A first-order differential equation is derived for the noise dynamics of ILOs. A single-ended injection-locked frequency divider (SILFD) is designed in a 0.5-/spl mu/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ba0c350ba4c69d9717be409c039f591
https://doi.org/10.1109/4.766815
https://doi.org/10.1109/4.766815
Autor:
H.R. Rategh, D.J. Eddleman, A. Shahani, S.S. Mohan, Min Xu, Thomas H. Lee, Mark Horowitz, D.K. Shaeffer, Chik Patrick Yue, H. Samavati, M. del Mar Hershenson
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:2232-2239
A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a369a55f1f5e3cb05c8963b08cc73ab5
https://doi.org/10.1109/4.735707
https://doi.org/10.1109/4.735707
Autor:
D.J. Eddleman, S.S. Mohan, A. Shahani, D.K. Shaeffer, Chik Patrick Yue, M. del Mar Hershenson, H.R. Rategh, Min Xu, H. Samavati, Thomas H. Lee
Publikováno v:
Hong Kong University of Science and Technology
This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f02e29e0630b9ce3962d21e660ef87b9
https://doi.org/10.1109/4.735706
https://doi.org/10.1109/4.735706
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72116d293e56b9460ca646b8ec95ea13
https://doi.org/10.1109/vlsic.1999.797245
https://doi.org/10.1109/vlsic.1999.797245
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
A fully integrated 5 GHz phase locked loop- (PLL-) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b70e648876972bf85118e71f0ac89f8b
https://doi.org/10.1109/vlsic.1999.797255
https://doi.org/10.1109/vlsic.1999.797255
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
A voltage controlled differential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0.24 /spl mu/m CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd68a6c742e8bff63874c5d3a84c836e
https://doi.org/10.1109/cicc.1999.777334
https://doi.org/10.1109/cicc.1999.777334