Zobrazeno 1 - 10
of 367
pro vyhledávání: '"H.E. Maes"'
Autor:
A. Shickova, Philippe Absil, E. San Andrés, R. Degraeve, D. Klenov, E Simoen, H.E. Maes, Guido Groeseneken, Peter Verheyen, B. Kaczer, P. Favia, Geert Eneman, M. Jurczak
Publikováno v:
IEEE Transactions on Electron Devices. 55:3432-3441
To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compr
Electrical Characterization of Leaky Charge-Trapping High-$\kappa$ MOS Devices Using Pulsed $Q$– $V$
Publikováno v:
IEEE Electron Device Letters. 28:436-439
A pulsed Q-V method enabling charge or capacitance measurements versus gate voltage of aggressively scaled, leaky (up to ~10 A/cm2 ), and charge-trapping high-kappa MOS devices is introduced. The method does not require RF structures and can be used
Autor:
Lionel Trojman, Maarten Rosmeulen, S. De Gendt, H.E. Maes, L.-A. Ragnarsson, V. Kaushik, M.M. Heyns, Guido Groeseneken, Barry O'Sullivan
Publikováno v:
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2007, 54 (3), pp.497-503. ⟨10.1109/TED.2006.890230⟩
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2007, 54 (3), pp.497-503. ⟨10.1109/TED.2006.890230⟩
The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradati
Autor:
Philippe Roussel, Guido Groeseneken, A. Kerber, Robin Degraeve, H.E. Maes, Luigi Pantisano, Thomas Kauerauf, Eduard A. Cartier, Udo Schwalke
Publikováno v:
IEEE Transactions on Electron Devices. 50:1261-1269
A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to
Publikováno v:
VLSI Design, Vol 13, Iss 1-4, Pp 459-463 (2001)
A careful calibration of a continuum process simulator is normally required to achieve a good agreement between simulated results and experimental dopant profiles. However, the validity of such a calibration procedure is often limited to a particular
Autor:
L. Haspeslagh, H.E. Maes, J. Van Houdt, Paul Hendrickx, Dirk Wellekens, L. Deferm, J. Tsouhlarakis
Publikováno v:
IEEE Transactions on Electron Devices. 47:2153-2160
In this paper, the performance and reliability characteristics of the 0.35 /spl mu/m/0.25 /spl mu/m High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fow
Autor:
Ben Kaczer, B. De Jaeger, M. Meuris, H.E. Maes, Tibor Grasser, Guido Groeseneken, Koen Martens
Publikováno v:
IEEE Electron Device Letters. 29:1364-1366
In this letter, the charge-pumping (CP) technique is validated for germanium MOSFETs. Effects of the smaller Ge bandgap on CP are discussed through both experiments and simulations. The standard CP setup with ~ 100-ns transition times at room tempera
Autor:
Thierry Conard, M.M. Heyns, Michel Houssa, Wim Deweerd, J.W. Maes, S. De Gendt, Marc Aoulaiche, Lionel Trojman, H.E. Maes, Guido Groeseneken
Publikováno v:
IEEE Electron Device Letters
IEEE Electron Device Letters, 2007, 28 (7), pp.613-615. ⟨10.1109/LED.2007.899435⟩
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (7), pp.613-615. ⟨10.1109/LED.2007.899435⟩
IEEE Electron Device Letters, 2007, 28 (7), pp.613-615. ⟨10.1109/LED.2007.899435⟩
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2007, 28 (7), pp.613-615. ⟨10.1109/LED.2007.899435⟩
Performance and negative-bias temperature instability (NBTI) on atomic-layer-deposited HfSiON metal-gated pMOSFETs are investigated. The impact of nitrogen incorporation either with plasma nitridation or NH3 anneal is studied and compared to the nonn
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1090-1095
This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current rea
Publikováno v:
Journal of Applied Physics. 83:4724-4733
Critical thickness hc has been calculated for capped and uncapped lattice mismatched II–VI semiconductor epilayers. Both the old equilibrium theory and the improved theory have been used. The calculated values are compared with the experimental dat