Zobrazeno 1 - 10
of 47
pro vyhledávání: '"H. Samavati"'
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 50:268-280
This paper first provides an overview of some recently ratified wireless local-area network (WLAN) standards before describing an illustrative 5-GHz WLAN receiver implementation. The receiver, built in a standard 0.25-/spl mu/m CMOS logic technology,
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:780-787
A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (IL
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:765-772
This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phas
Autor:
H.R. Rategh, D.J. Eddleman, A. Shahani, S.S. Mohan, Min Xu, Thomas H. Lee, Mark Horowitz, D.K. Shaeffer, Chik Patrick Yue, H. Samavati, M. del Mar Hershenson
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:2232-2239
A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator
Autor:
D.J. Eddleman, S.S. Mohan, A. Shahani, D.K. Shaeffer, Chik Patrick Yue, M. del Mar Hershenson, H.R. Rategh, Min Xu, H. Samavati, Thomas H. Lee
Publikováno v:
Hong Kong University of Science and Technology
This paper presents a 115-mW Global Positioning System radio receiver that is implemented in a 0.5-/spl mu/m CMOS technology. The receiver includes the complete analog signal path, comprising a low-noise amplifier, I-Q mixers, on-chip active filters,
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
This paper presents a 12.4 mW front-end for a 5 GHz wireless-LAN receiver fabricated in a 0.24 /spl mu/m CMOS technology. It consists of an LNA, mixers and an automatically tuned third-order filter controlled by a low-power PLL. The filter attenuates
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
A fully integrated 5 GHz phase locked loop- (PLL-) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. A voltage-controlled differential injection-locked frequency divider (VCDILFD) is used as the first frequency divider in t
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
A voltage controlled differential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0.24 /spl mu/m CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accu
Autor:
S.S. Mohan, Thomas H. Lee, A. Shahani, Maria del Mar Hershenson, Min Xu, H. Samavati, Chik Patrick Yue, D.K. Shaeffer, H.R. Rategh, D.J. Eddleman
Publikováno v:
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
The Global Positioning System (GPS) provides accurate positioning and timing information that is useful in many applications. In particular, portable consumer GPS applications require cheap compact low-power receivers. This 115 mW receiver, implement
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).