Zobrazeno 1 - 10
of 15
pro vyhledávání: '"H. Pournara"'
Autor:
Spiridon Nikolaidis, Konstantinos Tatas, Ilias Pappas, H. Pournara, V. Kalenteridis, Nikolaos Vassiliadis, Dimitrios Soudris, K. Siozos, G. Koutroumpezis, Antonios Thanailakis, Stylianos Siskos
Publikováno v:
Microprocessors and Microsystems. 29:247-259
In this paper a complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: the fine-grain reconfigurable hardware platform (FPGA) on which the logic is implement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::902f0801fabba3b1cb736e1a3c373edf
https://doi.org/10.1016/j.micpro.2004.09.001
https://doi.org/10.1016/j.micpro.2004.09.001
Autor:
H. Pournara, G. Koutroumpezis, Nikolaos Vassiliadis, Konstantinos Tatas, V. Kalenteridis, Konstantinos Siozios, Stilianos Siskos, Antonios Thanailakis, Ilias Pappas, Spiridon Nikolaidis, Dimitrios Soudris
Publikováno v:
IEICE Transactions on Information and Systems. :1369-1380
A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 μm CMOS technology. The detailed design an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fbe5c64c661d7bc87954ee7859243159
https://doi.org/10.1093/ietisy/e88-d.7.1369
https://doi.org/10.1093/ietisy/e88-d.7.1369
Autor:
Konstantinos Tatas, Spiridon Nikolaidis, Nikolaos Vassiliadis, Kostas Siozios, Ilias Pappas, V. Kalenteridis, G. Koutroumpezis, H. Pournara, Dimitrios Soudris, Stylianos Siskos, Antonios Thanailakis
Publikováno v:
Journal of Physics: Conference Series. 10:352-356
A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fadf257cfaf445d3b3021deb199fe567
https://doi.org/10.1088/1742-6596/10/1/086
https://doi.org/10.1088/1742-6596/10/1/086
Autor:
D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vasiliadis, V. Kalenteridis, H. Pournara, I. Pappas
Publikováno v:
Fine-and Coarse-Grain Reconfigurable Computing ISBN: 9781402065040
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3d560ef1ef5ce50593e200bdd11bf14
https://doi.org/10.1007/978-1-4020-6505-7_3
https://doi.org/10.1007/978-1-4020-6505-7_3
Autor:
Dimitrios Soudris, V. Kalenteridis, H. Pournara, Nikolaos Vassiliadis, Ilias Pappas, Stylianos Siskos, Spiridon Nikolaidis
Publikováno v:
Scopus-Elsevier
In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circui
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0e7c7da57f80213f5b5eb8a8838490a9
https://doi.org/10.1109/melcon.2004.1346810
https://doi.org/10.1109/melcon.2004.1346810
Autor:
Kostas Siozios, Spiridon Nikolaidis, H. Pournara, G. Koytroympezis, V. Kalenteridis, Dimitrios Soudris, Konstantinos Tatas, Ilias Pappas, Stylianos Siskos, Antonios Thanailakis
Publikováno v:
IPDPS
Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f9bf672bca75e985c21185e1a96c272
https://doi.org/10.1109/ipdps.2004.1303112
https://doi.org/10.1109/ipdps.2004.1303112
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540441434
PATMOS
PATMOS
Pass transistor logic is a promising alternative to conventional CMOS logic for low-power high-performance applications due to the decreased node capacitance and reduced transistor count it offers. However, the lack of supporting design automation to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8554ad635ff531f85e6a6a32965e46c
https://doi.org/10.1007/3-540-45716-x_23
https://doi.org/10.1007/3-540-45716-x_23
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