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Autor:
R. Itoh, S. Yamaguchi, M. Urano, Y. Miki, J. Yano, G. Inoue, H. Nabatani, K. Onizuka, S. Tsubata, K. Sokawa, J. Miyake, K. Ninomiya, T. Nishiyama
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
A 23GOPS programmable systolic array DSP for real-time video signal processing, called digital filtering array (DFA), is described. The DFA performs at the 129.6MHz clock rate with its 90 video processing element (VPE) array. HDTV (MUSE) signal decod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a40fd2ebae79d74c90638f88573d3f6
https://doi.org/10.1109/isscc.1997.585383
https://doi.org/10.1109/isscc.1997.585383
