Zobrazeno 1 - 10
of 59
pro vyhledávání: '"Gyu-Seob Jeong"'
Autor:
Byungjun Kang, Gyu-Seob Jeong, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Hyojun Kim, Han-Gon Ko, Moon-Chul Choi, Deog-Kyoon Jeong
Publikováno v:
IEEE Access, Vol 9, Pp 156789-156798 (2021)
A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both Tomlinson-Harashima precoding (THP) and feed-forward equalizatio
Externí odkaz:
https://doaj.org/article/a1222b27a2534eafae53be7a52e01438
Publikováno v:
IEEE Access, Vol 7, Pp 38035-38043 (2019)
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage
Externí odkaz:
https://doaj.org/article/0864df041941476f9510a96fbe7c11be
Autor:
Hyun-Chul Kim, Byungjun Kang, Han-Gon Ko, Moon-Chul Choi, Jeongho Hwang, Kwanseo Park, Hyungrok Do, Gyu-Seob Jeong, Deog-Kyoon Jeong
Publikováno v:
IEEE Access, Vol 9, Pp 156789-156798 (2021)
A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both Tomlinson-Harashima precoding (THP) and feed-forward equalizatio
Autor:
Yeojoon Youn, Sang-Hyeok Chu, Gyu-Seob Jeong, Taeik Kim, Deog-Kyoon Jeong, Jeongho Hwang, Woo-Seok Kim
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:1834-1838
This brief presents a programmable on-chip reference oscillator based on a slow-wave coplanar waveguide (S-CPW). The frequency is determined mainly by its geometric structure with floating stripes, thereby enjoying an advantage of being less sensitiv
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 66:4278-4286
This paper presents a transmit-side modulo-FIR equalizer (MFE) that is suitable for future high-throughput links. In a proposed PAM transceiver architecture, forward error correction (FEC) is employed to mitigate the BER degradation by the reduced SN
Publikováno v:
IEEE Access, Vol 7, Pp 38035-38043 (2019)
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage
Publikováno v:
Sensors, Vol 17, Iss 9, p 1962 (2017)
The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy elect
Externí odkaz:
https://doaj.org/article/1b17f69b994f4da488677f689c9ef5a3
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:1824-1828
This brief presents a single-ended asymmetric push-pull inverter for driving a vertical-cavity surface-emitting laser (VCSEL). The proposed driver topology features less power dissipation compared with commonly used differential CML-based drivers. Co
Autor:
Jiho Joo, Jeongho Hwang, Gyu-Seob Jeong, Kwanseo Park, Gyungock Kim, Dae-Young Yun, Jinhyung Lee, Hong Seok Choi, Kwangho Lee, Han-Gon Ko, Hyungrok Do, Daehyun Koh, Deog-Kyoon Jeong
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:1395-1399
This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel l
Autor:
Gyungock Kim, Jiho Joo, Woorham Bae, Jun-Eun Park, Jung Min Yoon, Jeongho Hwang, Gyu-Seob Jeong, Chang Soo Yoon, Deog-Kyoon Jeong
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:436-440
This brief presents a 32 Gb/s driver for a Mach–Zehnder modulator (MZM) and an electro-absorption modulator (EAM). A push–pull current-mode logic driver is chosen to achieve a better power efficiency and a large voltage swing. A double cascode wi