Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Gyounghwan Hyun"'
Autor:
Gyounghwan Hyun, Taewahn Kim
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 40:892-903
The retention flip-flop is an essential component in power gated circuits for retaining state during the sleep mode. In this article, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::25fdb846abbc5127b700d91d9ea095e0
https://doi.org/10.1109/tcad.2020.3013243
https://doi.org/10.1109/tcad.2020.3013243
Publikováno v:
ISLPED
It is generally known that a considerable portion of flip-flops in circuits is occupied by the ones with mux-feedback loop (called self-loop), which are the critical (inherently unavoidable) bottleneck in minimizing total (always-on) storage size for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fed685d756375a471fd5e2cc9f86ea0
https://doi.org/10.1145/3370748.3406556
https://doi.org/10.1145/3370748.3406556
Autor:
Taewhan Kim, Gyounghwan Hyun
Publikováno v:
ICCAD
Flip-flop's input data toggling based clock gating is one of the most widely used clock gating methods, in which one critical and inherent limitation is the sharp increase of gating logic as more flip-flops are gating. In this work, we propose a new
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abee3bec546ad8b9aeefe41855bc9a5b
https://doi.org/10.1109/iccad45719.2019.8942061
https://doi.org/10.1109/iccad45719.2019.8942061
Autor:
Gyounghwan Hyun, Taewhan Kim
Publikováno v:
ICCAD
In this paper, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for power gated circuits. Those are (1) the long wakeup delay caused by the senseless use of multi-bit retention flip-flops (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a47de0c82601ee00f4bd3ddd11ef7ca
https://doi.org/10.1109/iccad45719.2019.8942064
https://doi.org/10.1109/iccad45719.2019.8942064
Autor:
Chae Eun Rhee, Yongseok Jin, Jin-Su Jung, Gyounghwan Hyun, Seongyoon Kim, Eung Sup Kim, Hyuk-Jae Lee
Publikováno v:
ISCAS
The SoC presented in this paper integrates an H.264 encoder with an ISP (Image Signal Processor). It is currently implemented in an FPGA and processes an HD-size (1280 × 720) image at the speed of 15 fps with the operating clock frequency of 50 MHz.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73c7a4c3a63446d3a4bfb7dd6ce91a4c
https://doi.org/10.1109/iscas.2009.5118167
https://doi.org/10.1109/iscas.2009.5118167
Publikováno v:
2008 International SoC Design Conference.
In order to use a synchronous dynamic RAM (SDRAM) as the off-chip memory of an H.264/AVC encoder, this paper proposes an efficient SDRAM memory controller with an asynchronous bridge. With the proposed architecture, the SDRAM bandwidth is increased b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b37f2ebd8c91ed1ed177229641c5ff7
https://doi.org/10.1109/socdc.2008.4815697
https://doi.org/10.1109/socdc.2008.4815697
Publikováno v:
RTCSA
A large demand on memory bandwidth puts limitation on the performance improvement of an H.264/AVC decoder. In order to reduce the amount of frame memory access, this paper proposes a new memory architecture that uses a cache memory to store the data
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2cd0d3246e4fd7bd8e4863cbdb0759c
https://doi.org/10.1109/rtcsa.2007.74
https://doi.org/10.1109/rtcsa.2007.74
Autor:
Eung Sup Kim, Seongyoon Kim, GyoungHwan Hyun, Jinsu Jung, Chae Eun Rhee, Yongseok Jin, Hyuk-Jae Lee
Publikováno v:
2009 IEEE International Symposium on Circuits & Systems; 2009, p1936-1936, 1p
Publikováno v:
2008 International SoC Design Conference; 2008, pII-116, 1p