Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Gustavo E. Tellez"'
Publikováno v:
Proceedings of the 2022 International Symposium on Physical Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6056fb72f95445b603ebead47af1d5f9
https://doi.org/10.1145/3505170.3506726
https://doi.org/10.1145/3505170.3506726
Publikováno v:
DAC
Latch clustering is a critical stage to reduce power consumption at cost of timing disruption during a modern SoC design flow. However, most existing latch clustering researches mitigate timing disruptions by indirectly minimizing latch displacement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e64ac5c003214b32171e02f569cac4a2
https://doi.org/10.1109/dac18072.2020.9218617
https://doi.org/10.1109/dac18072.2020.9218617
Publikováno v:
DATE
Double patterning is a widely used technique for sub-22nm. Among various double patterning techniques, Self-Aligned Double Patterning (SADP) is a promising technique for good mask overlay control. Based on SADP, a new set of standard cells (T-cells)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::655d6368f41db46eea45247ac4ae22b9
https://doi.org/10.23919/date48585.2020.9116527
https://doi.org/10.23919/date48585.2020.9116527
Publikováno v:
ISPD
The continued delay of higher resolution alternatives for lithography, such as EUV, is forcing the continued adoption of multi-patterning solutions in new technology nodes, which include triple and quadruple patterning using several lithography-etch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c165632771019373c21b05a79e1d0df3
https://doi.org/10.1145/3177540.3178241
https://doi.org/10.1145/3177540.3178241
Publikováno v:
ISPD
Interconnect optimization, including buffer insertion and Steiner tree construction, continues to be a pillar technology that largely determines overall chip performance. Buffer insertion algorithms in published literature are mostly focused on optim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d57bcef31404a3fcac78f4036ab8559
https://doi.org/10.1145/3177540.3178237
https://doi.org/10.1145/3177540.3178237
Autor:
Christian Schulte, Markus Ahrens, Gustavo E. Tellez, Dirk Muller, Niko Klewinghaus, Sven Peyer, Michael Gester
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34:563-576
We present algorithms for routing in advanced technology nodes, used by BonnRoute (BR) to obtain efficient and almost design rule clean wire packings and pin access solutions. Designs with dense standard cell libraries in presence of complex industri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::494adc71f358c751fc02f18843b667c7
https://doi.org/10.1109/tcad.2014.2385755
https://doi.org/10.1109/tcad.2014.2385755
Autor:
Yaoguang Wei, Douglas Keller, Cliff Sze, Charles J. Alpert, Lakshmi Reddy, Sachin S. Sapatnekar, Zhuo Li, Natarajan Viswanathan, Gustavo E. Tellez, Andrew D. Huber
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 19:1-37
Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0a46dc6ca34b355ec2223388fb0c6c2
https://doi.org/10.1145/2566663
https://doi.org/10.1145/2566663
Autor:
S. Tsapepas, T. Schell, A. Bianchi, Michael S. Gray, Jeffrey A. Zitz, Erwin Behnen, R. Serton, James D. Warnock, Matthew T. Guzowski, L. Darden, D. Bradley, W. Ansley, Nagu Dhanwada, Robert M. Averill, Gustavo E. Tellez, Christopher J. Berry, L. Sigal, John D. Davis, Y.H. Chan, K. Acharya, M. DeHond, Michael R. Scheuermann, Hunter Shi, Tobias Werner, David H. Wolpert, D. Phan, G. Wiedemeier, K. G. Barkley Iii, Michael H. Wood, Sungjae Lee, R. Veerabhadraiah
Publikováno v:
IBM Journal of Research and Development. 62:10:1-10:14
The IBM z14 design was built with the 14-nm high-performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless enviro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c347292112257b360bda50c532d02964
https://doi.org/10.1147/jrd.2018.2800499
https://doi.org/10.1147/jrd.2018.2800499
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20:705-714
In this paper, we investigate reducing the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. We construct activity-driven clock trees wherein sections of the clock tree are turned off by ga
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b097ddf05cd2081fcd62b9212a8bc723
https://doi.org/10.1109/43.924824
https://doi.org/10.1109/43.924824
Autor:
Majid Sarrafzadeh, Gustavo E. Tellez
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16:333-342
In this paper, we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock slew rate (or rise time) constraint and a predefined clock tree. Using generalized properties of published CMOS timing m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::971324fab8c162eaa5198afd13f15c4d
https://doi.org/10.1109/43.602470
https://doi.org/10.1109/43.602470