Zobrazeno 1 - 10
of 59
pro vyhledávání: '"Guruprasad Katti"'
Autor:
Songbai Zhang, Ka Fai Chang, Guruprasad Katti, Rahul Dutta, Roshan Weerasekera, Surya Bhattacharya, Jun Zhou
Publikováno v:
IEEE Transactions on Electron Devices. 63:1182-1188
Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D IC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58e7b4e1d4b7100f27402167e24684f4
https://doi.org/10.1109/ted.2016.2522501
https://doi.org/10.1109/ted.2016.2522501
Autor:
Roshan Weerasekera, Surya Bhattacharya, Songbai Zhang, Soon Wee Ho, Jong-Kai Lin, Li Hong Yu, Guruprasad Katti, Rahul Dutta, Ka Fai Chang, Srinivasa Rao Vempati
Publikováno v:
IEEE Design & Test. 32:23-31
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration is reviewed. Polymer-based Cu-RDL interconnects provide a CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7a450201e70f601337d3d23e2867568
https://doi.org/10.1109/mdat.2015.2424429
https://doi.org/10.1109/mdat.2015.2424429
Autor:
Rahul Dutta, Ka Fai Chang, Joseph Romen Cubillo, Songbai Zhang, Guruprasad Katti, Hongyu Li, Roshan Weerasekera
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has bee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a999a412973be52a3d80e6d22e07f731
https://doi.org/10.1109/eptc.2016.7861479
https://doi.org/10.1109/eptc.2016.7861479
Publikováno v:
Solid-State Electronics. 53:256-265
The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson’s equation. 2D Poisson’s equation is solved
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c097bcfc350a540752ba17317501f588
https://doi.org/10.1016/j.sse.2008.12.001
https://doi.org/10.1016/j.sse.2008.12.001
Autor:
Rahul Dutta, Chang Ka Fai, Surya Bhattacharya, Roshan Weerasekera, Y. Weiliang, H. Y. Li, Guruprasad Katti, Soon Wee Ho
Publikováno v:
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
For both power/ground and data carrying TSVs, TSV resistance is preferred to be as low as possible. Power/ground TSVs should exhibit larger TSV capacitance so that TSV can act as a decoupling capacitor while data TSVs should exhibit low TSV capacitan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cafd91ec670f62418cc40d93d3b780c
https://doi.org/10.1109/edssc.2015.7285097
https://doi.org/10.1109/edssc.2015.7285097
Publikováno v:
IEEE Transactions on Electron Devices. 51:1169-1177
A threshold voltage model for mesa-isolated fully depleted silicon-on-insulator (FDSOI) MOSFETs, based on the analytical solution of three-dimensional (3-D) Poisson's equation is presented for the first time in this paper. The separation of variables
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::20250628346f59f4e9da04a779dee26e
https://doi.org/10.1109/ted.2004.830648
https://doi.org/10.1109/ted.2004.830648
Autor:
Surya Bhattacharya, Roshan Weerasekera, Songbai Zhang, Cheng Jin, Guruprasad Katti, Ka Fai Chang
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
This paper proposes a 60 GHz wideband Yagi-Uda antenna for 2.5 Through Silicon Interposer (TSI) platform. The integrated antenna comprises two parts: a wideband Marchand balun and a differential Yagi-Uda antenna. Marchand balun transfers the balanced
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1f6d85da43d0baec3f25a9655f62079
https://doi.org/10.1109/eptc.2014.7028344
https://doi.org/10.1109/eptc.2014.7028344
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
This paper presents the design, integration and characterization of integrated passive devices (IPDs) on low cost through silicon interposer (LC-TSI). The performances of symmetrical spiral and 3D inductors are presented and analyzed in this paper. R
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8887b27cb4130d2255d4a596996164b
https://doi.org/10.1109/eptc.2014.7028270
https://doi.org/10.1109/eptc.2014.7028270
Autor:
S. W. Ho, Tai Chong Chai, Guruprasad Katti, Pei Siang Lim, Mian Zhi Ding, Surya Bhattacharya, Daniel Ismail Cereno
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
In this paper, the fabrication process and results of 2.5D through silicon interposer (TSI) package using polymer based RDL and chip-on-wafer (CoW) stacking-first approach is presented. The through silicon interposer is fabricated on a 300 mm silicon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5af803e651fe408998a3279683a73d8e
https://doi.org/10.1109/eptc.2014.7028352
https://doi.org/10.1109/eptc.2014.7028352
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
This paper describes the electrical characteristics of the fine pitch interconnects in silicon carrier systems. The characteristics of such interconnects are explored and a typical FPGA-memory system is compared viz-a-viz with a traditional PCB syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86f99fe76528f36cfbd8e4ceda574b22
https://doi.org/10.1109/eptc.2012.6507115
https://doi.org/10.1109/eptc.2012.6507115