Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Gurkaynak, F. K."'
Autor:
Cevrero, A., Athanasopoulos, Panagiotis, Parandeh-Afshar, Hadi, Verma, A. K., Niaki, H. S. A., Nicopoulos, Chrysostomos A., Gurkaynak, F. K., Brisk, P., Leblebici, Y., Ienne, P.
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems
ACM Trans.Reconfigurable Technol.Syst.
ACM Trans.Reconfigurable Technol.Syst.
Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b8e6018fac5e8d8b8f177591f31f6975
http://gnosis.library.ucy.ac.cy/handle/7/42963
http://gnosis.library.ucy.ac.cy/handle/7/42963
Autor:
Temiz Y., Gurkaynak F. K., Terrettaz S., Vogel H., De Micheli G., Leblebici Y., GUIDUCCI, CARLOTTA, BENINI, LUCA
This paper presents a switched-capacitor (SC) current integrator circuit for impedance measurement of tethered bilayer lipid membrane (tBLM) biosensors. The circuit comprises a small number of high performance components enabling enhanced experimenta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______4094::fed107bb235a5306634fb6443d732dfb
http://hdl.handle.net/11585/81768
http://hdl.handle.net/11585/81768
Akademický článek
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We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______185::479a96d0d16000895b51d78308b669cd
https://infoscience.epfl.ch/record/53630
https://infoscience.epfl.ch/record/53630
Publikováno v:
Scopus-Elsevier
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::48cf8ca4b84f2669105b9cfa095435f9
http://www.scopus.com/inward/record.url?eid=2-s2.0-84945922688&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-84945922688&partnerID=MN8TOARS
Autor:
Niaki, S. H. A., Cevrero, A., Brisk, P., Nicopoulos, Chrysostomos A., Gurkaynak, F. K., Leblebici, Y., Lenne, P.
Publikováno v:
Embedded Systems Week 2008-Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08
CASES
CASES
The Field Programmable Compressor Tree (FPCT) is a programmable compressor tree (e.g., a Wallace or Dadda Tree) intended for integration in an FPGA or other reconfigurable device. This paper presents a design space exploration (DSE) method that can b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e0a383de02a5807a8937cd4d6e642f09
https://infoscience.epfl.ch/record/129027
https://infoscience.epfl.ch/record/129027