Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Guogui Deng"'
Autor:
Zhengfang Liu, Xinyi Hu, Kareem Madkour, Qijian Wan, Joe Kwan, Guogui Deng, Aliaa Kabeel, Shirui Yu, Meili Zhang, Gensheng Gao, Wael ElManhawy, Mudan Wang, Chunshan Du
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XII.
As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42ccc04d9e3a51cedd6bd419f660473d
https://doi.org/10.1117/12.2297296
https://doi.org/10.1117/12.2297296
Publikováno v:
ECS Transactions. 60:173-178
Double patterning using 193 nm immersion lithography has been adapted as the solution to enable 20 nm technology nodes. In the Back end, Litho Etch Litho Etch (LELE) is considered as the most suitable process for this technology. The overlay control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::042acd71c8031f30b401a22f30bd4d9c
https://doi.org/10.1149/06001.0173ecst
https://doi.org/10.1149/06001.0173ecst
Autor:
Xin Yao, Guogui Deng, Xuelong Shi, Bin Xing, Jingan Hao, Qiang Zhang, Qiang Wu, BoXiu Cai, Gaorong Li, Yi-Shih Lin
Publikováno v:
ECS Transactions. 60:205-212
Critical dimension uniformity (CDU) of hole layer is becoming more and more crucial alongside with the technology node being driven into 28 nm and beyond, since the critical dimension (CD) variation of 2-dimensional (2D) hole pattern is inherently la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8acd1cf47010e5f94cf492e991cd1a5
https://doi.org/10.1149/06001.0205ecst
https://doi.org/10.1149/06001.0205ecst
Publikováno v:
ECS Transactions. 60:225-229
When the semiconductor technology enters the 28 nm and below, defectivity becomes increasingly difficult to detect and remove. In this paper, we studied one kind of water-spot like defect which was first suspected to originate from the immersion lith
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee13cf397bf1ed26266fa9a77e433561
https://doi.org/10.1149/06001.0225ecst
https://doi.org/10.1149/06001.0225ecst
Publikováno v:
ECS Transactions. 52:221-226
Since the device integration and relating lithography process progressively increasing in complexity, more integrated approach to process control has been very necessary. There is more function in scanners that can be used to improve process window,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::151600c9e28c4b4ee40ca124a278913e
https://doi.org/10.1149/05201.0221ecst
https://doi.org/10.1149/05201.0221ecst
Autor:
Qiang Wu, Weiming He, He Kaiting, Yi-Shih Lin, Yuntao Jiang, Guogui Deng, Lihong Xiao, Bin Xing, Jingan Hao, Qiang Zhang, Xuelong Shi, Chang Liu
Publikováno v:
SPIE Proceedings.
In this paper, we present a study on the overlay (OVL) shift issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI shift (AEI: After E
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9d374cc0ba8462d90527884a8322d5d
https://doi.org/10.1117/12.2220013
https://doi.org/10.1117/12.2220013
Publikováno v:
2016 China Semiconductor Technology International Conference (CSTIC).
In this paper, we present a study on the overlay (OVL) offset issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI offset (AEI: After
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff26dfb378b4013cb03846578a3a0bc1
https://doi.org/10.1109/cstic.2016.7463984
https://doi.org/10.1109/cstic.2016.7463984
Autor:
Shijian Zhang, Nannan Zhang, Qiang Wu, Yanlei Zu, Huayong Hu, Gaorong Li, Manhua Shen, Chang Liu, Xuelong Shi, Guogui Deng, Bin Xing, Weiming He, Yuntao Jiang, Yi-Shih Lin, Jingan Hao, Qiang Zhang, Liwan Yue
Publikováno v:
SPIE Proceedings.
As the technology node of semiconductor industry is being driven into more advanced 28 nm and beyond, the critical dimension (CD) error budget at after-development inspection (ADI) stage and its control are more and more important and difficult (1-4)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30841d52ed16800add11c9c7cb344e9d
https://doi.org/10.1117/12.2086093
https://doi.org/10.1117/12.2086093
Publikováno v:
2015 China Semiconductor Technology International Conference.
Moving to the 28 nm technology node and beyond, contact to poly overlay requirement becomes more and more stringent in order to achieve manufacturable static random access memory (SRAM) yield. Typically, a 6 nm or even better on product overlay (OPO)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220a8acb2c313700e739ed45ad614bb4
https://doi.org/10.1109/cstic.2015.7153357
https://doi.org/10.1109/cstic.2015.7153357
Publikováno v:
2015 China Semiconductor Technology International Conference.
Scanning Electron Microscope (SEM) image blurring issue is reported at via level after developing inspection (ADI) measurement in dual damascene process. The root cause is the existence of non-uniform electric field at measurement locations. To find
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e93f627afd3b4a03098d93b9d39f93e4
https://doi.org/10.1109/cstic.2015.7153367
https://doi.org/10.1109/cstic.2015.7153367